Patents by Inventor Wei Hao

Wei Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096787
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes an interconnection structure over a semiconductor substrate and a conductive pillar over the interconnection structure. The conductive pillar has a protruding portion extending towards the semiconductor substrate from a lower surface of the conductive pillar. The semiconductor device structure also includes an upper conductive via between the conductive pillar and the interconnection structure and a lower conductive via between the upper conductive via and the interconnection structure. The lower conductive via is electrically connected to the conductive pillar through the upper conductive via. The conductive pillar extends across opposite sidewalls of the upper conductive via and opposite sidewalls of the lower conductive via. A top view of an entirety of the second conductive via is separated from a top view of an entirety of the protruding portion.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Ming-Da CHENG, Wei-Hung LIN, Hui-Min HUANG, Chang-Jung HSUEH, Po-Hao TSAI, Yung-Sheng LIN
  • Publication number: 20240096779
    Abstract: A flexible package is provided. The flexible package includes a first carrier and a second carrier. The second carrier is electrically connected to the first carrier. The second carrier is at least partially embedded in the first carrier, and an electrical connection interface between the first carrier and the second carrier is within the first carrier.
    Type: Application
    Filed: September 20, 2022
    Publication date: March 21, 2024
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Wei-Hao CHANG
  • Publication number: 20240097833
    Abstract: Techniques are described for hybrid automatic repeat request acknowledgement (HARQ-ACK) information generation techniques for group common shared channels, such as one or more physical downlink shared channels (PDSCHs).
    Type: Application
    Filed: November 30, 2023
    Publication date: March 21, 2024
    Inventors: Xiaolong GUO, Wei GOU, Jing SHI, Xing LIU, Peng HAO, Xingguang WEI
  • Publication number: 20240098724
    Abstract: The present disclosure describes methods, system, and devices for collision resolution in configuring time-frequency resource in a half-duplex and/or full-duplex telecommunication system. The method includes receiving, by a user equipment (UE), a first message which is used to resolve a collision between a first transmission in a first frequency resource region and a second transmission in a second frequency resource region, wherein the first and second transmissions overlap in a time domain; and determining, by the UE based on the first message, to transmit one of the first transmission and the second transmission, wherein transmission directions of the first transmission and the second transmission are different.
    Type: Application
    Filed: November 28, 2023
    Publication date: March 21, 2024
    Applicant: ZTE Corporation
    Inventors: Jing SHI, Xianghui HAN, Wei GOU, Shuaihua KOU, Peng HAO
  • Publication number: 20240093700
    Abstract: A fan cage assembly includes a cage and a handle mechanism, the handle mechanism includes a mount member including a mount portion and an extension portion respectively located at different sides of the cage and an operative member movably disposed on the extension portion of the mount member.
    Type: Application
    Filed: February 17, 2023
    Publication date: March 21, 2024
    Inventor: WEI-HAO CHEN
  • Publication number: 20240097831
    Abstract: Techniques are described to supporting transmission on any serving cell, carrier, or bandwidth part (BWP). An example wireless communication method includes receiving, by a first device from a second device, a first control information that schedules a first transmission on a first cell with the first device, where the first control information indicates a first hybrid automatic repeat request (HARQ) entity associated with the first transmission; and performing an operation to process the first control information.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 21, 2024
    Applicant: ZTE Corporation
    Inventors: Shuaihua KOU, Peng HAO, Wei GOU, Junfeng ZHANG
  • Patent number: 11935757
    Abstract: A method of manufacturing a semiconductor device includes forming a first layer of a first planarizing material over a patterned surface of a substrate, forming a second layer of a second planarizing material over the first planarizing layer, crosslinking a portion of the first planarizing material and a portion of the second planarizing material, and removing a portion of the second planarizing material that is not crosslinked. In an embodiment, the method further includes forming a third layer of a third planarizing material over the second planarizing material after removing the portion of the second planarizing material that is not crosslinked. The third planarizing material can include a bottom anti-reflective coating or a spin-on carbon, and an acid or an acid generator. The first planarizing material can include a spin-on carbon, and an acid, a thermal acid generator or a photoacid generator.
    Type: Grant
    Filed: April 10, 2023
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yen-Hao Chen, Wei-Han Lai, Ching-Yu Chang, Chin-Hsiang Lin
  • Publication number: 20240088033
    Abstract: A method of forming a semiconductor device is provided. A transistor is formed at a first side of the substrate and a first dielectric layer is formed aside the transistor. A first metal via is formed through the first dielectric layer and aside the transistor. A first interconnect structure is formed over the first side of the substrate and electrically connected to the transistor and the first metal via. The substrate is thinned from a second side of the substrate. A capacitor is formed at the second side of the substrate and a second dielectric layer is formed aside the capacitor. A second metal via is formed through the second dielectric layer and the substrate and electrically connected to the first metal via.
    Type: Application
    Filed: March 20, 2023
    Publication date: March 14, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chao-Kai Chan, Chung-Hao Tsai, Chuei-Tang WANG, Wei-Ting Chen
  • Publication number: 20240088145
    Abstract: Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.
    Type: Application
    Filed: November 27, 2023
    Publication date: March 14, 2024
    Inventors: Zhi-Chang Lin, Wei-Hao Wu, Jia-Ni Yu, Chih-Hao Wang, Kuo-Cheng Ching
  • Publication number: 20240088182
    Abstract: In some embodiments, an image sensor is provided. The image sensor includes a photodetector disposed in a semiconductor substrate. A wave guide filter having a substantially planar upper surface is disposed over the photodetector. The wave guide filter includes a light filter disposed in a light filter grid structure. The light filter includes a first material that is translucent and has a first refractive index. The light filter grid structure includes a second material that is translucent and has a second refractive index less than the first refractive index.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Cheng Yu Huang, Chun-Hao Chuang, Chien-Hsien Tseng, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Wen-Chien Yu, Ting-Cheng Chang, Wen-Hau Wu, Chih-Kung Chang
  • Publication number: 20240088078
    Abstract: Packaged memory devices including memory devices hybrid bonded to logic devices and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a first memory die including a first memory cell electrically coupled to a first word line; a second memory cell electrically coupled to the first word line; and a first interconnect structure electrically coupled to the first word line; a circuitry die including a second interconnect structure, a first conductive feature of the first interconnect structure being bonded to a second conductive feature of the second interconnect structure through metal-to-metal bonds; and a word line driver electrically coupled to the first word line between the first memory cell and the second memory cell, the word line driver being electrically coupled to the first word line through the first interconnect structure and the second interconnect structure.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Chung-Hao Tsai, Yih Wang, Wei-Ting Chen, Chuei-Tang Wang, Chen-Hua Yu
  • Publication number: 20240088050
    Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Inventors: Chen-Hua Yu, Wei-Kang Hsieh, Shih-Wei Chen, Tin-Hao Kuo, Hao-Yi Tsai
  • Publication number: 20240089960
    Abstract: The present disclosure describes methods, system, and devices for resolving directional conflicts in a sub-band full duplex (SBFD) telecommunication system. The method includes obtaining a first communication occasion and a second communication occasion configured or scheduled in opposite directions to overlap in a time domain or with a gap in the time domain less than a threshold; determining whether to cancel at least a portion of the first communication occasion or to cancel at least a portion of the second communication occasion; in response to determining to cancel at least the portion of the second communication occasion, canceling at least the portion of the second communication occasion and performing the first communication occasion; and in response to determining to cancel at least the portion of the first communication occasion, canceling at least the portion of the first communication occasion and performing the second communication occasion.
    Type: Application
    Filed: November 20, 2023
    Publication date: March 14, 2024
    Applicant: ZTE Corporation
    Inventors: Peng HAO, Wei GOU, Jing SHI
  • Publication number: 20240090044
    Abstract: Techniques are described for performing feedback by a communication device. An example wireless communication method includes receiving, by a communication device, X shared channels from a network device, where the X shared channels are located in between a first random access channel (RACH) instance and a second RACH instance in time domain, where the second RACH instance includes Y RACH occasions in time domain, where X and Y are integers, and where Y is greater than or equal to X; and transmitting, by the communication device, a preamble in at least one RACH occasion from the Y RACH occasions, where the preamble indicates exactly one of: (1) a feedback associated with a shared channel from the X shared channels, or (2) a random access.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Inventors: Peng HAO, Xing LIU, Jian LI, Jing SHI, Shuaihua KOU, Wei GOU
  • Patent number: 11929788
    Abstract: Disclosed is a microwave photonic Ising machine, including: a closed loop including a phase and electro-optical conversion module and a storage, correlation and photoelectric conversion module connected in turn; a laser light source configured to generate and input an optical signal to the phase and electro-optical conversion module; and a microwave pulse local oscillator source configured to generate and input a microwave pulse signal to the phase and electro-optical conversion module. The phase and electro-optical conversion module is configured to modulate the microwave pulse signal, the optical signal, and a phase-specific two-phase microwave pulse spin electrical signal input from the storage, correlation and photoelectric conversion module to obtain and input a phase-specific two-phase microwave pulse spin optical signal to the storage, correlation and photoelectric conversion module for storage and correlation.
    Type: Grant
    Filed: November 22, 2021
    Date of Patent: March 12, 2024
    Assignee: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
    Inventors: Ming Li, Tengfei Hao, Yao Meng, Qizhuang Cen, Yitang Dai, Nuannuan Shi, Wei Li
  • Patent number: 11929434
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 12, 2024
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Patent number: 11926901
    Abstract: A method for fabricating nonenzymatic glucose sensor, which comprises steps of: (a) providing a bottom substrate; (b) preparing a graphene layer on the bottom substrate; (c) depositing plural amount of zinc oxide (ZnO) seed crystals on the graphene layer; (d) growing the ZnO seed crystals into columnar nanorods with hydrothermal method; (e) coating a thin film of cuprous oxide (Cu2O) on the surface of the ZnO nanorods by electrochemistry-based electrodeposition; and (f) grafting single-walled carbon nanotubes (SWCNTs) on surface of the Cu2O thin film, by using Nafion fixative composited with SWCNTs. The structure of the above sensor, therefore, comprises a bottom substrate and other components orderly assembled on it, including, from inside to outside, a graphene layer, plural amount of ZnO nanorods, a Cu2O thin film, plural amount of SWCNTs, and the Nafion fixative. Accordingly, the sensor has advantages of low cost, rapid response, and easy for preservation.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: March 12, 2024
    Assignee: NATIONAL YUNLIN UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Hsi-Chao Chen, Wei-Rong Su, Yun-Cheng Yeh, Chun-Hao Chang
  • Patent number: 11929585
    Abstract: A mixer-based microwave signal generation device is provided, and the mixer-based microwave signal generation device includes a microwave local oscillator source, a mixer, a first filter, a laser, an electro-optic modulator, an optical signal delayer, a photodetector, a second filter, an amplifier and a passive power divider.
    Type: Grant
    Filed: September 29, 2021
    Date of Patent: March 12, 2024
    Assignee: INSTITUTE OF SEMICONDUCTORS, CHINESE ACADEMY OF SCIENCES
    Inventors: Ming Li, Tengfei Hao, Qizhuang Cen, Yitang Dai, Nuannuan Shi, Wei Li
  • Publication number: 20240079443
    Abstract: A light emitting plate, a wiring plate and a display device are provided. The light emitting plate includes light emitting units. Each light emitting unit includes a light emitting sub-unit including a connection line unit and a light emitting diode chip connected with the connection line unit. The connection line unit includes electrical contact pairs, and each electrical contact pairs includes a first electrode contact and a second electrode contact; in each connection line unit, the second electrode contacts are electrically connected with each other, the first electrode contacts are electrically connected with each other, and only one electrical contact pairs in each connection line unit is connected with the light emitting diode chip; in each connection line unit, at least two first electrode contacts are arranged adjacent to each other, and at least two first electrode contacts are arranged between at least two second electrode contacts.
    Type: Application
    Filed: November 13, 2023
    Publication date: March 7, 2024
    Applicant: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ming YANG, Wei HAO, Qibing GU, Guofeng HU, Lingyun SHI, Minghua XUAN, Can ZHANG
  • Publication number: 20240080180
    Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.
    Type: Application
    Filed: December 20, 2022
    Publication date: March 7, 2024
    Inventors: Chih-Fan HSU, Wei-Chao CHEN, Jing-Lun Huang, Ming-Ching Chang, Feng-Hao Liu