Abstract: An image sensing device includes a germanium sensor within a semiconductor body and a metalens formed in the back side of the semiconductor body. The metalens is structured to focus infrared light on the germanium sensor and may have a lower profile than an equivalent microlens. Optionally, the metalens is combined with a microlens to achieve a desired focal length. The metalens, or the metalens in combination with a microlens, overcomes a manufacturing process limitation on the focal length of the microlens, which in turn eliminates the need for, or reduces the thickness of, a spacer between the microlens and the germanium sensor. Eliminating the spacer or reducing its thickness improves the angular response of the image sensing device.

Abstract: The present disclosure provides a sensing package. The sensing package includes a carrier configured to face an object to be inspected and an emitter disposed adjacent to the carrier. The emitter is configured to emit a first light propagating in a first direction. The sensing package further includes a component configured to change the first light into a second light propagating in a second direction different from the first direction. An optical module and a method for detecting light are also provided.

Abstract: The present disclosure provides IL-10 muteins and use of IL-10 muteins in fusion proteins. The IL-10 mutein or the fusion protein comprise one or more substitution on amino acids in position 104, position 107, and a combination thereof, relative to amino acids of wild-type IL-10. Advantageously, the IL-10 mutein or the fusion protein thereof are provided with reduced aggregation potency during purification and extended half-life.

Abstract: Various embodiments of the present disclosure are directed towards an image sensor device including a first image sensor element and a second image sensor element disposed within a substrate. An interconnect structure is disposed along a front-side surface of the substrate and comprises a plurality of conductive wires, a plurality of conductive vias, and a first absorption structure. The first image sensor element is configured to generate electrical signals from electromagnetic radiation within a first range of wavelengths. The second image sensor element is configured to generate electrical signals from the electromagnetic radiation within a second range of wavelengths that is different than the first range of wavelengths. The second image sensor element is laterally adjacent to the first image sensor element. Further, the first image sensor element overlies the first absorption structure and is spaced laterally between opposing sidewalls of the first absorption structure.

Abstract: A power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.

Abstract: Some embodiments relate to a CMOS image sensor disposed on a substrate. A plurality of pixel regions comprising a plurality of photodiodes, respectively, are configured to receive radiation that enters a back-side of the substrate. A boundary deep trench isolation (BDTI) structure is disposed at boundary regions of the pixel regions, and includes a first set of BDTI segments extending in a first direction and a second set of BDTI segments extending in a second direction perpendicular to the first direction to laterally surround the photodiode. The BDTI structure comprises a first material. A pixel deep trench isolation (PDTI) structure is disposed within the BDTI structure and overlies the photodiode. The PDTI structure comprises a second material that differs from the first material, and includes a first PDTI segment extending in the first direction such that the first PDTI segment is surrounded by the BDTI structure.

Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.

Abstract: The present disclosure relates to an integrated chip including a substrate and a pixel. The pixel includes a photodetector. The photodetector is in the substrate. The integrated chip further includes a first inner trench isolation structure and an outer trench isolation structure that extend into the substrate. The first inner trench isolation structure laterally surrounds the photodetector in a first closed loop. The outer trench isolation structure laterally surrounds the first inner trench isolation structure along a boundary of the pixel in a second closed loop and is laterally separated from the first inner trench isolation structure. Further, the integrated chip includes a scattering structure that is defined, at least in part, by the first inner trench isolation structure and that is configured to increase an angle at which radiation impinges on the outer trench isolation structure.

Abstract: The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.

Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Photoresist layer is selectively exposed to radiation, and selectively exposed photoresist layer developed. Photoresist composition includes photoactive compound, crosslinker, copolymer.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having an active region as the substrate includes a medium-voltage (MV) region and a low-voltage (LV) region, forming a first divot adjacent to one side of the active region, forming a second divot adjacent to another side of the active region, forming a first liner in the first divot and the second divot and on the substrate of the MV region and LV region, forming a second liner on the first liner, and then removing the second liner, the first liner, and the substrate on the LV region for forming a fin-shaped structure.

Abstract: A power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.

Abstract: The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.

Abstract: A semiconductor device including a semiconductor die, a first conductive pad, a second conductive pad, a first connector structure and a second connector structure is provided. The first conductive pad is disposed on the semiconductor die, wherein the first conductive pad has a first lateral dimension. The second conductive pad is disposed on the semiconductor die, wherein the second conductive pad has a second lateral dimension. The first connector structure is disposed on the first conductive pad, wherein the first connector structure has a third lateral dimension greater than the first lateral dimension. The second connector structure is disposed on the second conductive pad, wherein the second connector structure has a fourth lateral dimension smaller than the second lateral dimension.

Abstract: The disclosure provides an eye state assessment method and an electronic device. The method includes: obtaining an optic disc image area from a first fundus photography and generating multiple optic cup-to-disc ratio assessment results by multiple first models based on the optic disc image area; obtaining a first assessment result of an eye based on the optic cup-to-disc ratio assessment results; performing multiple data augmentation operations on the first fundus photography to generate multiple second fundus photographies; generating multiple retinal nerve fiber layer (RNFL) defect assessment results by multiple second models based on the second fundus photographies; obtaining a second assessment result of the eye based on the RNFL defect assessment results; and obtaining an optic nerve assessment result of the eye based on the first assessment result and the second assessment result.

Abstract: A method includes removing a dummy gate to leave a trench between gate spacers, forming a gate dielectric extending into the trench, depositing a metal layer over the gate dielectric, with the metal layer including a portion extending into the trench, depositing a filling region into the trench, with the metal layer have a first and a second vertical portion on opposite sides of the filling region, etching back the metal layer, with the filling region at least recessed less than the metal layer, and remaining parts of the portion of the metal layer forming a gate electrode, depositing a dielectric material into the trench, and performing a planarization to remove excess portions of the dielectric material. A portion of the dielectric material in the trench forms at least a portion of a dielectric hard mask over the gate electrode.

Abstract: A method for fabricating a semiconductor device includes the steps of forming a fin-shaped structure on a substrate, forming a first trench and a second trench in the fin-shaped structure, forming a first dielectric layer in the first trench and the second trench, removing part of the first dielectric layer, forming a second dielectric layer in the first trench and the second trench to form a first single diffusion break (SDB) structure and a second SDB structure, and then forming a gate structure on the fin-shaped structure, the first SDB structure, and the second SDB structure.

Abstract: A system for verifying edited image includes: a producer terminal device configured to tile a source image for a plurality of smaller tiled images with individual source image hash values to accordingly calculate an integrated source image hash value, and to execute digitally signing to generate an image tag pair; an editor terminal device configured to receive the image tag pair, to divide the source image into these smaller tiled images according to a tile configuration, to edit part of the smaller tiled images, to include the rest part of these smaller tiled images to generate an edited integral image and further calculate an integrated edit image hash value, and to execute digitally signing to generate a zero-knowledge proof (ZKP) assurance; and, a user terminal device configured to receive the ZKP assurance to accordingly verify whether or not the edited integral image is generated by editing the source image.

Abstract: A semiconductor device package and a method of manufacturing the same are provided. The semiconductor device package includes a first circuit layer, a second circuit layer under the first circuit layer, a first electronic component between the first circuit layer and the second circuit layer and connected to the first circuit layer and a sub-package between the first circuit layer and the second circuit layer and connected to the second circuit layer. The sub package comprises a second electronic component under the first electronic component and a conductive structure configured to dissipate heat generated from the first electronic component.

Abstract: A semiconductor die includes a semiconductor substrate, an interconnect structure, and a conductive bump. The interconnect structure is disposed on and electrically connected to the semiconductor substrate. The interconnect structure includes stacked interconnect layers. Each of the stacked interconnect layers includes a dielectric layer and an interconnect wiring embedded in the dielectric layer. The interconnect wiring of a first interconnect layer among the stacked interconnect layers further includes a first via and second vias. The first via electrically connected to the interconnect wiring. The second vias connected to the interconnect wiring, and the first via and the second vias are located on a same level height. The conductive bump is disposed on the interconnect structure. The conductive bump includes a base portion and a protruding portion connected to the base portion, and the base portion is between the protruding portion and the first via.