Patents by Inventor Wei-Hao Chiu

Wei-Hao Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240210775
    Abstract: An electronic device is provided. The electronic device includes a substrate, a thin-film transistor, a transparent conductive layer, a first organic layer, and a second organic layer. The thin-film transistor is disposed on the substrate and includes a drain electrode. The transparent conductive layer is disposed on the drain electrode and is electrically connected to the drain electrode. The first organic layer is disposed between the drain electrode and the transparent conductive layer. The first organic layer has a through-hole. The second organic layer is disposed in the through-hole. The electronic device has a cell gap. There is a first distance between an upper surface of the first organic layer and an upper surface of the second organic layer. The cell gap and the first distance conform to the following formula: 0<the first distance?0.8Ă—the cell gap.
    Type: Application
    Filed: November 17, 2023
    Publication date: June 27, 2024
    Inventors: Ming-Jou TAI, Chia-Hao TSAI, Yi-Shiuan CHERNG, Wei-Yen CHIU
  • Publication number: 20240213134
    Abstract: An electronic package is provided, in which an electronic element is disposed on a carrier with a circuit layer, and an encapsulation layer encapsulating the electronic element has an opening exposing the circuit layer, where a metal structure can be contact-bonded on a wall surface of the opening, and a conductive element is formed on the metal structure and electrically connected to the circuit layer. Therefore, no gap is formed between the conductive element and the wall surface of the opening, such that the DC resistance of the conductive element can be reduced.
    Type: Application
    Filed: April 28, 2023
    Publication date: June 27, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien CHIU, Wen-Jung TSAI, Wei-Hao LI, Chih-Yi LIAO, Cheng-Wei HSU, Chih-Yuan TSAI, Ko-Wei CHANG, Guo-Yu WU
  • Publication number: 20240186373
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Application
    Filed: February 7, 2024
    Publication date: June 6, 2024
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Publication number: 20240171162
    Abstract: A phase error compensation circuit and a method for compensating a phase error between a reference clock and a feedback clock are provided. The phase error compensation circuit includes a first programmable delay circuit, a second programmable delay circuit and at least one swapping circuit. The first programmable delay circuit provides a first delay. The second programmable delay circuit provides a second delay. At a present cycle, the first delay is unchanged, wherein the swapping circuit applies the first delay to the feedback clock for generating a compensated feedback clock and applies the second delay to the reference clock for generating a compensated reference clock. At a next cycle, the second delay is unchanged, where the swapping circuit applies the second delay to the feedback clock for generating the compensated feedback clock and applies the first delay to the reference clock for generating the compensated reference clock.
    Type: Application
    Filed: August 15, 2023
    Publication date: May 23, 2024
    Applicant: MEDIATEK INC.
    Inventors: Wei-Hao Chiu, Song-Yu Yang, Ang-Sheng Lin
  • Publication number: 20240142833
    Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Applicant: Innolux Corporation
    Inventors: Wei-Yen Chiu, Ming-Jou Tai, You-Cheng Lu, Yi-Shiuan Cherng, Yi-Hsiu Wu, Chia-Hao Tsai, Yung-Hsun Wu
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Patent number: 11223362
    Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: January 11, 2022
    Assignee: MEDIATEK INC.
    Inventors: Wei-Hao Chiu, Ang-Sheng Lin, Tzu-Chan Chueh
  • Publication number: 20210359687
    Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.
    Type: Application
    Filed: April 28, 2021
    Publication date: November 18, 2021
    Inventors: Wei-Hao CHIU, Ang-Sheng LIN, Tzu-Chan CHUEH
  • Patent number: 11152891
    Abstract: An inductor-capacitor (LC) oscillator with an embedded second harmonic filter and an associated dual core oscillator are provided. The LC oscillator includes a first transistor, a second transistor, a first part-one inductor, a second part-one inductor, a part-one capacitor, a part-two inductor and at least one part-two capacitor. A first end of the first part-one inductor and a first end of the second part-one inductor are coupled to gate terminals of the second transistor and the first transistor, respectively. The part-one capacitor is coupled between the first end of the first part-one inductor and the first end of the second part-one inductor. The part-two inductor is coupled between a second end of the first part-one inductor and a second end of the second part-one inductor. The at least one part-two capacitor is coupled to drain terminals of the first transistor and the second transistor.
    Type: Grant
    Filed: December 7, 2020
    Date of Patent: October 19, 2021
    Assignee: MEDIATEK INC.
    Inventors: Hao-Wei Huang, Ang-Sheng Lin, Wei-Hao Chiu
  • Publication number: 20210320622
    Abstract: An inductor-capacitor (LC) oscillator with an embedded second harmonic filter and an associated dual core oscillator are provided. The LC oscillator includes a first transistor, a second transistor, a first part-one inductor, a second part-one inductor, a part-one capacitor, a part-two inductor and at least one part-two capacitor. A first end of the first part-one inductor and a first end of the second part-one inductor are coupled to gate terminals of the second transistor and the first transistor, respectively. The part-one capacitor is coupled between the first end of the first part-one inductor and the first end of the second part-one inductor. The part-two inductor is coupled between a second end of the first part-one inductor and a second end of the second part-one inductor. The at least one part-two capacitor is coupled to drain terminals of the first transistor and the second transistor.
    Type: Application
    Filed: December 7, 2020
    Publication date: October 14, 2021
    Inventors: Hao-Wei Huang, Ang-Sheng Lin, Wei-Hao Chiu
  • Patent number: 10778145
    Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: September 15, 2020
    Assignee: MEDIATEK INC.
    Inventors: Yu-Li Hsueh, Po-Chun Huang, Ang-Sheng Lin, Wei-Hao Chiu
  • Publication number: 20200212843
    Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.
    Type: Application
    Filed: November 12, 2019
    Publication date: July 2, 2020
    Inventors: Yu-Li Hsueh, Po-Chun Huang, Ang-Sheng Lin, Wei-Hao Chiu
  • Patent number: 10425038
    Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.
    Type: Grant
    Filed: September 11, 2016
    Date of Patent: September 24, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wei-Hao Chiu, Tzu-Chan Chueh, Ang-Sheng Lin
  • Patent number: 9948265
    Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: April 17, 2018
    Assignee: MEDIATEK INC.
    Inventors: Kun-Yin Wang, Wei-Hao Chiu, Ang-Sheng Lin
  • Publication number: 20180062002
    Abstract: A solar cell includes a semiconductor substrate, one or more bus bar electrode, and a plurality of finger electrodes. The bus bar electrode and the finger electrodes are disposed on the semiconductor substrate. Conventionally, in a process of forming the finger electrodes by utilizing screen printing, offset may occur. Consequently, the finger electrodes cannot be connected to the bus bar electrode. According to the provided solar cell, the bus bar electrode is formed by using patterned silver and aluminum, to manufacture a wider bus bar electrode than the bus bar electrode in the conventional solar cell without increasing silver consumption, thereby resolving the problem of offset.
    Type: Application
    Filed: July 24, 2017
    Publication date: March 1, 2018
    Applicant: NEO SOLAR POWER CORP.
    Inventors: Wei-Hao CHIU, Je-Wei LIN, Wei-Ming CHEN, Chie-Sheng LIU, Shan-Chuang PEI, Wei-Chih HSU
  • Publication number: 20170111009
    Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.
    Type: Application
    Filed: September 11, 2016
    Publication date: April 20, 2017
    Inventors: Wei-Hao Chiu, Tzu-Chan Chueh, Ang-Sheng Lin
  • Patent number: 9541939
    Abstract: A switching current source circuit is provided. A current source drains a bias current from a power supply via a first mirror transistor. A second mirror transistor has a source coupled to the power supply, a gate coupled to the gate of the first mirror transistor, and a drain for providing an output current. A switch is coupled between the gates of the first and second mirror transistors, and has a control terminal for receiving a control signal. A first capacitor is coupled between the gate of the second mirror transistor and the voltage generating unit. A second capacitor is coupled between the gate of the second mirror transistor and a ground. The voltage generating unit selectively provides a first voltage or a second voltage different from the first voltage to the first capacitor according to the control signal.
    Type: Grant
    Filed: May 30, 2014
    Date of Patent: January 10, 2017
    Assignee: MEDIATEK INC.
    Inventors: Liang-Ting Kuo, Wei-Hao Chiu
  • Publication number: 20160336914
    Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.
    Type: Application
    Filed: February 22, 2016
    Publication date: November 17, 2016
    Inventors: Kun-Yin Wang, Wei-Hao Chiu, Ang-Sheng Lin
  • Patent number: 9473147
    Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.
    Type: Grant
    Filed: March 3, 2015
    Date of Patent: October 18, 2016
    Assignee: MEDIATEK INC.
    Inventors: Wei-Hao Chiu, Ang-Sheng Lin, Kun-Yin Wang
  • Publication number: 20160261273
    Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.
    Type: Application
    Filed: March 3, 2015
    Publication date: September 8, 2016
    Inventors: Wei-Hao Chiu, Ang-Sheng Lin, Kun-Yin Wang