Patents by Inventor Wei-Hao Chiu
Wei-Hao Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142833Abstract: An electronic device includes a substrate, a driving element, a first insulating layer, a pixel electrode layer, and a common electrode layer. The driving element is disposed on the substrate. The first insulating layer is disposed on the driving element. The pixel electrode layer is disposed on the first insulating layer. The first insulating layer comprises a hole, and the pixel electrode layer is electrically connected to the driving element through the hole. The common electrode layer is disposed on the pixel electrode layer. The common electrode layer comprises a slit, and the slit has an edge, and the edge is disposed in the hole.Type: ApplicationFiled: January 11, 2024Publication date: May 2, 2024Applicant: Innolux CorporationInventors: Wei-Yen Chiu, Ming-Jou Tai, You-Cheng Lu, Yi-Shiuan Cherng, Yi-Hsiu Wu, Chia-Hao Tsai, Yung-Hsun Wu
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Patent number: 11923409Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.Type: GrantFiled: August 5, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
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Patent number: 11223362Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.Type: GrantFiled: April 28, 2021Date of Patent: January 11, 2022Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Ang-Sheng Lin, Tzu-Chan Chueh
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Publication number: 20210359687Abstract: A phase-locked loop (PLL) circuit is provided in the invention. The PLL circuit includes a first DTC, a first selection circuit, and a second selection circuit. The first DTC receives a first delay control signal to dither a reference signal or a feedback signal. The first selection circuit is coupled to the first DTC. The first selection circuit receives the reference signal and the feedback signal, and according to the selection signal, transmits the reference signal or the feedback signal to the first DTC. The second selection circuit is coupled to the first DTC and the first selection circuit. The second selection circuit determines the output paths of an output reference signal or an output feedback signal according to the selection signal.Type: ApplicationFiled: April 28, 2021Publication date: November 18, 2021Inventors: Wei-Hao CHIU, Ang-Sheng LIN, Tzu-Chan CHUEH
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Patent number: 11152891Abstract: An inductor-capacitor (LC) oscillator with an embedded second harmonic filter and an associated dual core oscillator are provided. The LC oscillator includes a first transistor, a second transistor, a first part-one inductor, a second part-one inductor, a part-one capacitor, a part-two inductor and at least one part-two capacitor. A first end of the first part-one inductor and a first end of the second part-one inductor are coupled to gate terminals of the second transistor and the first transistor, respectively. The part-one capacitor is coupled between the first end of the first part-one inductor and the first end of the second part-one inductor. The part-two inductor is coupled between a second end of the first part-one inductor and a second end of the second part-one inductor. The at least one part-two capacitor is coupled to drain terminals of the first transistor and the second transistor.Type: GrantFiled: December 7, 2020Date of Patent: October 19, 2021Assignee: MEDIATEK INC.Inventors: Hao-Wei Huang, Ang-Sheng Lin, Wei-Hao Chiu
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Publication number: 20210320622Abstract: An inductor-capacitor (LC) oscillator with an embedded second harmonic filter and an associated dual core oscillator are provided. The LC oscillator includes a first transistor, a second transistor, a first part-one inductor, a second part-one inductor, a part-one capacitor, a part-two inductor and at least one part-two capacitor. A first end of the first part-one inductor and a first end of the second part-one inductor are coupled to gate terminals of the second transistor and the first transistor, respectively. The part-one capacitor is coupled between the first end of the first part-one inductor and the first end of the second part-one inductor. The part-two inductor is coupled between a second end of the first part-one inductor and a second end of the second part-one inductor. The at least one part-two capacitor is coupled to drain terminals of the first transistor and the second transistor.Type: ApplicationFiled: December 7, 2020Publication date: October 14, 2021Inventors: Hao-Wei Huang, Ang-Sheng Lin, Wei-Hao Chiu
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Patent number: 10778145Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.Type: GrantFiled: November 12, 2019Date of Patent: September 15, 2020Assignee: MEDIATEK INC.Inventors: Yu-Li Hsueh, Po-Chun Huang, Ang-Sheng Lin, Wei-Hao Chiu
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Publication number: 20200212843Abstract: A voltage controlled oscillator includes a first inductor, a second inductor, a first metal oxide semiconductor (MOS) transistor, a second MOS transistor, and an inductor-capacitor (LC) tank circuit. A first end of the first inductor and a first end of the second inductor are coupled to a first power rail. A drain node of the first MOS transistor is coupled to a second end of the first inductor. A drain node of the second MOS transistor is coupled to a second end of the second inductor. Source nodes of the first MOS transistor and the second MOS transistor are coupled to a second power rail. The LC tank circuit is coupled to gate nodes of the first MOS transistor and the second MOS transistor, wherein energy is magnetically pumped into the LC tank circuit through the first inductor and the second inductor.Type: ApplicationFiled: November 12, 2019Publication date: July 2, 2020Inventors: Yu-Li Hsueh, Po-Chun Huang, Ang-Sheng Lin, Wei-Hao Chiu
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Patent number: 10425038Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.Type: GrantFiled: September 11, 2016Date of Patent: September 24, 2019Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Tzu-Chan Chueh, Ang-Sheng Lin
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Patent number: 9948265Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.Type: GrantFiled: February 22, 2016Date of Patent: April 17, 2018Assignee: MEDIATEK INC.Inventors: Kun-Yin Wang, Wei-Hao Chiu, Ang-Sheng Lin
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Publication number: 20180062002Abstract: A solar cell includes a semiconductor substrate, one or more bus bar electrode, and a plurality of finger electrodes. The bus bar electrode and the finger electrodes are disposed on the semiconductor substrate. Conventionally, in a process of forming the finger electrodes by utilizing screen printing, offset may occur. Consequently, the finger electrodes cannot be connected to the bus bar electrode. According to the provided solar cell, the bus bar electrode is formed by using patterned silver and aluminum, to manufacture a wider bus bar electrode than the bus bar electrode in the conventional solar cell without increasing silver consumption, thereby resolving the problem of offset.Type: ApplicationFiled: July 24, 2017Publication date: March 1, 2018Applicant: NEO SOLAR POWER CORP.Inventors: Wei-Hao CHIU, Je-Wei LIN, Wei-Ming CHEN, Chie-Sheng LIU, Shan-Chuang PEI, Wei-Chih HSU
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Publication number: 20170111009Abstract: An oscillator for generating oscillation signals at two output terminals includes an inductor coupled between the two output terminals, a capacitor coupled between the two output terminals, two P-type transistors and two N-type transistors. Source electrodes of the two P-type transistors are coupled to a supply voltage, and gate electrodes of the two P-type transistors are coupled to the two output terminals, respectively. Source electrodes of the two N-type transistors are coupled to a supply voltage, gate electrodes of the two N-type transistors are coupled to the two output terminals, respectively, and drain electrodes of the two N-type transistors are coupled to drain electrodes of the two P-type transistors, respectively. In addition, the drain electrodes of the two N-type transistors are coupled to two internal nodes of the inductor.Type: ApplicationFiled: September 11, 2016Publication date: April 20, 2017Inventors: Wei-Hao Chiu, Tzu-Chan Chueh, Ang-Sheng Lin
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Patent number: 9541939Abstract: A switching current source circuit is provided. A current source drains a bias current from a power supply via a first mirror transistor. A second mirror transistor has a source coupled to the power supply, a gate coupled to the gate of the first mirror transistor, and a drain for providing an output current. A switch is coupled between the gates of the first and second mirror transistors, and has a control terminal for receiving a control signal. A first capacitor is coupled between the gate of the second mirror transistor and the voltage generating unit. A second capacitor is coupled between the gate of the second mirror transistor and a ground. The voltage generating unit selectively provides a first voltage or a second voltage different from the first voltage to the first capacitor according to the control signal.Type: GrantFiled: May 30, 2014Date of Patent: January 10, 2017Assignee: MEDIATEK INC.Inventors: Liang-Ting Kuo, Wei-Hao Chiu
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Publication number: 20160336914Abstract: An inductor capacitor (LC) tank includes a first inductor and a first tunable capacitive array. The first inductor has a first terminal and a second terminal, and the first tunable capacitive array has a first terminal and a second terminal. The first tunable capacitive array is at a path branching from a first point between the first terminal and the second terminal of the first inductor, the first terminal of the first tunable capacitive array is coupled to the first point, and the second terminal of the first tunable capacitive array and the second terminal of the first inductor are coupled to a reference voltage.Type: ApplicationFiled: February 22, 2016Publication date: November 17, 2016Inventors: Kun-Yin Wang, Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 9473147Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.Type: GrantFiled: March 3, 2015Date of Patent: October 18, 2016Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Ang-Sheng Lin, Kun-Yin Wang
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Publication number: 20160261273Abstract: A frequency dividing apparatus includes: a plurality of latching devices arranged to selectively generate an output signal having a first oscillating frequency or a second oscillating frequency different from the first oscillating frequency according to an input clock signal and a first reset signal; and a controlling device arranged to generate the first reset signal at least according to a programming input signal; wherein the first reset signal is arranged to reset a first latching device in the plurality of latching devices to make the plurality of latching devices to generate the output signal having the second oscillating frequency.Type: ApplicationFiled: March 3, 2015Publication date: September 8, 2016Inventors: Wei-Hao Chiu, Ang-Sheng Lin, Kun-Yin Wang
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Patent number: 9397557Abstract: A charge pump at least includes a current source, a first switch, a second switch, a level-shift circuit, and a capacitor. The first switch is coupled between the current source and an internal node. The capacitor is coupled between the internal node and the level-shift circuit. The second switch is coupled between the internal node and an output node. The first switch performs a closing-and-opening operation and the level-shift circuit performs a level-shift operation while the second switch is kept open and the internal node is isolated from the output node. The operating range of the charge pump is effectively widened by using the proposed design.Type: GrantFiled: May 15, 2014Date of Patent: July 19, 2016Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 9331569Abstract: A current generating circuit, which comprises: a first capacitor, comprising a first terminal and a second terminal; a second capacitor, comprising a first terminal and a second terminal; a first charge adjusting path, arranged for adjusting charges of the first capacitor according to a first charge adjusting voltage; a second charge adjusting path, arranged for adjusting charges of the second capacitor according to the first charge adjusting voltage; and a current generating path, coupled to the first capacitor and the second capacitor, arranged for generating a target current based on a difference between a first voltage provided by the first capacitor and a second voltage provided by the second capacitor.Type: GrantFiled: January 14, 2015Date of Patent: May 3, 2016Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Ang-Sheng Lin
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Patent number: 9298199Abstract: A voltage generating circuit comprising: an output current generating circuit, generating an output current, such that an output voltage is generated at an output terminal, according to an output voltage control signal; a comparing device, comprising a first input terminal receiving a reference voltage, a second input terminal receiving a feedback voltage related with the output voltage, and an output terminal outputting the output voltage control signal according to the reference voltage and the feedback voltage; an adjustable voltage dropping circuit, comprising a first terminal coupled to the second input terminal, and a second terminal coupled to the output terminal; and a current source, for generating a predetermined current to the first terminal of the adjustable voltage dropping circuit, thereby the feedback voltage is generated at the first terminal of the adjustable voltage dropping circuit. The predetermined current flows through the adjustable voltage dropping circuit to the output terminal.Type: GrantFiled: August 13, 2014Date of Patent: March 29, 2016Assignee: MEDIATEK INC.Inventors: Wei-Hao Chiu, Kun-Yin Wang, Ang-Sheng Lin
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Publication number: 20160048145Abstract: A voltage generating circuit comprising: an output current generating circuit, generating an output current, such that an output voltage is generated at an output terminal, according to an output voltage control signal; a comparing device, comprising a first input terminal receiving a reference voltage, a second input terminal receiving a feedback voltage related with the output voltage, and an output terminal outputting the output voltage control signal according to the reference voltage and the feedback voltage; an adjustable voltage dropping circuit, comprising a first terminal coupled to the second input terminal, and a second terminal coupled to the output terminal; and a current source, for generating a predetermined current to the first terminal of the adjustable voltage dropping circuit, thereby the feedback voltage is generated at the first terminal of the adjustable voltage dropping circuit. The predetermined current flows through the adjustable voltage dropping circuit to the output terminal.Type: ApplicationFiled: August 13, 2014Publication date: February 18, 2016Inventors: Wei-Hao Chiu, Kun-Yin Wang, Ang-Sheng Lin