Abstract: A voltage generating circuit comprising: an output current generating circuit, generating an output current, such that an output voltage is generated at an output terminal, according to an output voltage control signal; a comparing device, comprising a first input terminal receiving a reference voltage, a second input terminal receiving a feedback voltage related with the output voltage, and an output terminal outputting the output voltage control signal according to the reference voltage and the feedback voltage; an adjustable voltage dropping circuit, comprising a first terminal coupled to the second input terminal, and a second terminal coupled to the output terminal; and a current source, for generating a predetermined current to the first terminal of the adjustable voltage dropping circuit, thereby the feedback voltage is generated at the first terminal of the adjustable voltage dropping circuit. The predetermined current flows through the adjustable voltage dropping circuit to the output terminal.

Abstract: A switching current source circuit is provided. A current source drains a bias current from a power supply via a first mirror transistor. A second mirror transistor has a source coupled to the power supply, a gate coupled to the gate of the first mirror transistor, and a drain for providing an output current. A switch is coupled between the gates of the first and second mirror transistors, and has a control terminal for receiving a control signal. A first capacitor is coupled between the gate of the second mirror transistor and the voltage generating unit. A second capacitor is coupled between the gate of the second mirror transistor and a ground. The voltage generating unit selectively provides a first voltage or a second voltage different from the first voltage to the first capacitor according to the control signal.

Abstract: A charge pump at least includes a current source, a first switch, a second switch, a level-shift circuit, and a capacitor. The first switch is coupled between the current source and an internal node. The capacitor is coupled between the internal node and the level-shift circuit. The second switch is coupled between the internal node and an output node. The first switch performs a closing-and-opening operation and the level-shift circuit performs a level-shift operation while the second switch is kept open and the internal node is isolated from the output node. The operating range of the charge pump is effectively widened by using the proposed design.

Abstract: A signal mixing circuit which mixes input signal(s) and oscillation signal(s) by mixer block(s) to provide a mixed signal. Each mixer block includes a summing node and a circuit unit; the summing node is arranged to provide a sum signal by summing an input signal and an oscillation signal, and the circuit unit is arranged to alternate between a first state and a second state in response to alternating of the oscillation signal; wherein the circuit unit is arranged to provide driving contribution to the mixed signal in response to the sum signal during the first state, and to stop providing driving contribution during the second state. An associated converter, e.g., a digital-to-analog converter, is also disclosed.

Abstract: A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed.

Abstract: A receiver circuit, e.g., a low-IF receiver, including two mixing paths. The two mixing paths scale an input signal respectively by two mixing gains and shift phase of the input signal respectively by two mixing phase offsets to provide two mixed signals. The two mixing gains and the two mixing phase offsets are arranged to produce an amplitude adjustment between amplitudes of the two mixed signals and a phase difference of 90 degrees plus a phase adjustment between phases of the two mixed signals. With the amplitude adjustment and/or the phase adjustment properly tuned to nonzero value(s) in association with band-pass response of the receiver circuit, image rejection can be achieved and optimized. Associated method is also disclosed.

Abstract: A frequency tracking circuit is disclosed. The frequency tracking circuit includes an edge selector, a phase-frequency processor and a digital controlled oscillator. The edge selector receives a data signal and feedback clock signal and sequentially outputs a data edge signal and a feedback-clock-edge signal. The phase-frequency processor receives the data edge signal and the feedback-clock-edge signal and outputs a frequency adjusting digital signal after executing differential operation according to a first phase difference and a second phase difference. The digital controlled oscillator receives the frequency adjusting digital signal so as to adjust frequency of the feedback clock signal. The phase-frequency processor outputs a frequency tracking signal to the edge selector, wherein the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal.

Abstract: A frequency tracking circuit is disclosed. The frequency tracking circuit includes an edge selector, a phase-frequency processor and a digital controlled oscillator. The edge selector receives a data signal and feedback clock signal and sequentially outputs a data edge signal and a feedback-clock-edge signal. The phase-frequency processor receives the data edge signal and the feedback-clock-edge signal and outputs a frequency adjusting digital signal after executing differential operation according to a first phase difference and a second phase difference. The digital controlled oscillator receives the frequency adjusting digital signal so as to adjust frequency of the feedback clock signal. The phase-frequency processor outputs a frequency tracking signal to the edge selector, wherein the edge selector utilizes the frequency tracking signal for acquiring the data edge signal and utilizes the data edge signal for acquiring the feedback-clock-edge signal.

Abstract: A receiver circuit, e.g., a low-IF receiver, including two mixing paths. The two mixing paths scale an input signal respectively by two mixing gains and shift phase of the input signal respectively by two mixing phase offsets to provide two mixed signals. The two mixing gains and the two mixing phase offsets are arranged to produce an amplitude adjustment between amplitudes of the two mixed signals and a phase difference of 90 degrees plus a phase adjustment between phases of the two mixed signals. With the amplitude adjustment and/or the phase adjustment properly tuned to nonzero value(s) in association with band-pass response of the receiver circuit, image rejection can be achieved and optimized. Associated method is also disclosed.

Abstract: A mixer for providing a mixed signal by mixing an input signal and an oscillation signal, comprising a follower and a switch. The follower is arranged to conduct a driving contribution from a bias terminal to an output terminal following a signal at an input terminal, wherein the input terminal and the bias terminal are respectively coupled to the input signal and the oscillation signal, and the output terminal is arranged to output the mixed signal. The switch is arranged to selectively conduct the output terminal to a reference level in response to alternating of the oscillation signal. An associated signal circuit is also disclosed.

Abstract: A signal mixing circuit which mixes input signal(s) and oscillation signal(s) by mixer block(s) to provide a mixed signal. Each mixer block includes a summing node and a circuit unit; the summing node is arranged to provide a sum signal by summing an input signal and an oscillation signal, and the circuit unit is arranged to alternate between a first state and a second state in response to alternating of the oscillation signal; wherein the circuit unit is arranged to provide driving contribution to the mixed signal in response to the sum signal during the first state, and to stop providing driving contribution during the second state. An associated converter, e.g., a digital-to-analog converter, is also disclosed.

Abstract: Methods for fabricating electrode structures on a substrate are presented. The fabrication method includes providing a substrate with a patterned metal layer thereon, defining an electrode area. A passivation glue is formed on the patterned metal layer. An electrode layer is formed in the electrode area. A filling process is performed to deposit nano metal oxides on the electrode layer to extensively fill the entire electrode area.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.

Abstract: Methods for fabricating electrode structures on a substrate are presented. The fabrication method includes providing a substrate with a patterned metal layer thereon, defining an electrode area. A passivation glue is formed on the patterned metal layer. An electrode layer is formed in the electrode area. A filling process is performed to deposit nano metal oxides on the electrode layer to extensively fill the entire electrode area.

Abstract: A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.

Abstract: A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.

Abstract: A phase locked loop includes a voltage controlled oscillator operable to generate an output signal corresponding to a reference signal in response to a control voltage signal outputted by a filter in response to a current signal, and a variable frequency divider operable to perform frequency division on the output signal using a variable divisor so as to generate a divided feedback signal. A charge pump outputs the current signal in response to a phase detecting output from a phase/frequency detector indicating phases of the divided feedback signal and the reference signal. A phase error comparator outputs, in accordance with the phase detecting output, a digital output indicating whether the divided feedback signal lags or leads the reference signal and further indicating a phase difference between the divided feedback signal and the reference signal.