Patents by Inventor Wei-Hsiang Ma
Wei-Hsiang Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210089700Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a first type-two transistor, a second type-two transistor, a third type-one transistor, a fourth type-one transistor, and a fifth type-one transistor. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The first active-region of the third type-one transistor is connected with an active-region of the first type-one transistor. The second active-region and the gate of the third type-one transistor are connected together. The first active-region of the fifth type-one transistor is connected with the gate of the third type-one transistor. The second active-region of the fifth type-one transistor is configured to have a first supply voltage of a second power supply.Type: ApplicationFiled: December 8, 2020Publication date: March 25, 2021Inventors: Chi-Yu LU, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Jerry Chang Jui KAO, Pin-Dai SUE, Jiun-Jia HUANG, Yu-Ti SU, Wei-Hsiang MA
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Publication number: 20200395938Abstract: A multiplexer circuit includes first and second fins each extending in an X-axis direction. First, second, third and fourth gates extend in a Y-axis direction perpendicular to the X-axis direction and contact the first and second fins. The first, second, third and fourth gates are configured to receive first, second, third and fourth data signals, respectively. Fifth, sixth, seventh and eighth gates extend in the Y-axis direction and contact the first and second fins, the fifth, sixth, seventh and eighth gates, and are configured to receive the first, second, third and fourth select signals, respectively. An input logic circuit is configured to provide an output at an intermediate node. A ninth gate extends in the Y-axis direction and contacts the first and second fins. An output logic circuit is configured to provide a selected one of the first, second, third and fourth data signals at an output terminal.Type: ApplicationFiled: May 26, 2020Publication date: December 17, 2020Inventors: Chi-Lin Liu, Shang-Chih Hsieh, Jian-Sing Li, Wei-Hsiang Ma, Yi-Hsun Chen, Cheok-Kei Lei
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Patent number: 10867104Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a third type-one transistor, and a fourth type-one transistor. The first type-one transistor and the third type-one transistor are in the first portion of the type-one active zone. The integrated circuit includes a first type-two transistor in the first portion of the type-two active zone. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a gate configured to have the first supply voltage of a second power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor.Type: GrantFiled: August 23, 2019Date of Patent: December 15, 2020Inventors: Chi-Yu Lu, Ting-Wei Chiang, Hui-Zhong Zhuang, Pin-Dai Sue, Jerry Chang Jui Kao, Yu-Ti Su, Wei-Hsiang Ma, Jiun-Jia Huang
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Publication number: 20200350916Abstract: A circuit includes a level shifter circuit, an output circuit and a feedback circuit. The level shifter circuit is coupled to a first voltage supply, and is configured to receive at least an enable signal, a first input signal or a second input signal. The level shifter circuit is configured to generate at least a first signal responsive to at least the enable signal or the first input signal. The output circuit is coupled to at least the level shifter circuit and the first voltage supply, is configured to receive the first signal, and to generate at least an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit, the output circuit and the first voltage supply, and is configured to receive the enable signal, an inverted enable signal and the set of feedback signals.Type: ApplicationFiled: July 22, 2020Publication date: November 5, 2020Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
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Publication number: 20200272778Abstract: A method includes: identifying ad hoc groups of elementary standard cells recurrent in a layout diagram, selecting one of the recurrent ad hoc groups (selected group) such that: the elementary standard cells in the selected group have connections representing a corresponding logic circuit; each elementary standard cell representing a logic gate; each ad hoc group has a number of transistors and a first number of logic gates; and the selected group providing a logical function. The method includes generating one or more macro standard cells such that: each macro standard cell has a number of transistors which is smaller than the number of transistors of the corresponding ad hoc group; or each macro standard cell has a second number of logic gates different than the first number of logic gates of the corresponding ad hoc group. The method also includes adding macro standard cells to the set of standard cells.Type: ApplicationFiled: May 12, 2020Publication date: August 27, 2020Inventors: Chi-Lin LIU, Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Lee-Chung LU, Shang-Chih HSIEH, Wei-Hsiang MA
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Patent number: 10735001Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.Type: GrantFiled: March 26, 2019Date of Patent: August 4, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yu-Lun Ou, Jerry Chang Jui Kao, Lee-Chung Lu, Ruei-Wun Sun, Shang-Chih Hsieh, Ji-Yung Lin, Wei-Hsiang Ma, Yung-Chen Chien
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Patent number: 10664565Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one ad hoc group amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.Type: GrantFiled: March 27, 2018Date of Patent: May 26, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Lee-Chung Lu, Shang-Chih Hsieh, Wei-Hsiang Ma
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Publication number: 20200074039Abstract: An integrated circuit includes a first type-one transistor, a second type-one transistor, a third type-one transistor, and a fourth type-one transistor. The first type-one transistor and the third type-one transistor are in the first portion of the type-one active zone. The integrated circuit includes a first type-two transistor in the first portion of the type-two active zone. The first type-one transistor has a gate configured to have a first supply voltage of a first power supply. The first type-two transistor has a gate configured to have a second supply voltage of the first power supply. The third type-one transistor has a gate configured to have the first supply voltage of a second power supply. The third type-one transistor has a first active-region conductively connected with an active-region of the first type-one transistor.Type: ApplicationFiled: August 23, 2019Publication date: March 5, 2020Inventors: Chi-Yu LU, Ting-Wei CHIANG, Hui-Zhong ZHUANG, Pin-Dai SUE, Jerry Chang Jui KAO, Yu-Ti SU, Wei-Hsiang MA, Jiun-Jia HUANG
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Publication number: 20190319624Abstract: A circuit includes an input circuit, a level shifter circuit, an output circuit and a feedback circuit. The input circuit is coupled to a first voltage supply, and configured to receive a first input signal, and to generate a second input signal. The level shifter circuit is coupled to the input circuit, and configured to receive an enable signal, the first input signal or the second input signal, and to generate a first signal responsive to the enable signal or the first input signal. The output circuit is coupled to the level shifter circuit, and is configured to receive the first signal, and to generate an output signal or a set of feedback signals responsive to the first signal. The feedback circuit is coupled to the level shifter circuit and output circuit, and is configured to receive the enable signal or the set of feedback signals.Type: ApplicationFiled: March 26, 2019Publication date: October 17, 2019Inventors: Yu-Lun OU, Jerry Chang Jui KAO, Lee-Chung LU, Ruei-Wun SUN, Shang-Chih HSIEH, Ji-Yung LIN, Wei-Hsiang MA, Yung-Chen CHIEN
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Publication number: 20190305761Abstract: A circuit includes a slave latch including a first input and an output, the first input being coupled to a master latch, and a retention latch including a second input coupled to the output. The master latch and the slave latch are configured to operate in a first power domain having a first power supply voltage level, the retention latch is configured to operate in a second power domain having a second power supply voltage level different from the first power supply voltage level, and the circuit further includes a level shifter configured to shift a signal level from one of the first power supply voltage level or the second power supply voltage level to the other of the first power supply voltage level or the second power supply voltage level.Type: ApplicationFiled: March 6, 2019Publication date: October 3, 2019Inventors: Kai-Chi HUANG, Jerry Chang Jui KAO, Chi-Lin LIU, Lee-Chung LU, Shang-Chih HSIEH, Wei-Hsiang MA, Yung-Chen CHIEN
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Publication number: 20180336293Abstract: A method (of expanding a set of standard cells which comprise a library, the library being stored on a non-transitory computer-readable medium) includes: selecting one amongst ad hoc groups of elementary standard cells which are recurrent resulting in a selected group such that the elementary standard cells in the selected group having connections so as to represent a corresponding logic circuit, each elementary standard cell representing a logic gate, and the selected group corresponding providing a selected logical function which is representable correspondingly as a selected Boolean expression; generating, in correspondence to the selected group, one or more macro standard cells; and adding the one or more macro standard cells to, and thereby expanding, the set of standard cells; and wherein at least one aspect of the method is executed by a processor of a computer.Type: ApplicationFiled: March 27, 2018Publication date: November 22, 2018Inventors: Chi-Lin LIU, Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Lee-Chung LU, Shang-Chih HSIEH, Wei-Hsiang MA
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Patent number: 10002654Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.Type: GrantFiled: June 26, 2015Date of Patent: June 19, 2018Assignee: Intel CorporationInventors: Jaydeep P Kulkarni, Pramod Kolar, Ankit Sharma, Subho Chatterjee, Karthik Subramanian, Farhana Sheikh, Wei-Hsiang Ma
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Patent number: 9812189Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.Type: GrantFiled: June 4, 2015Date of Patent: November 7, 2017Assignee: Intel CorporationInventors: Pramod Kolar, Wei-Hsiang Ma, Gunjan H. Pandya
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Publication number: 20160379694Abstract: In some embodiments, disclosed is a wordline boosting technique using a self-timed capacitive charge boosting approach.Type: ApplicationFiled: June 26, 2015Publication date: December 29, 2016Applicant: Intel CorporationInventors: JAYDEREP KULKARNI, PRAMOD KOLAR, ANKIT SHARMA, SUBHO CHATTERJEE, KARTHIK SUBRAMANIAN, FARHANA SHEIKH, WEI-HSIANG MA
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Publication number: 20160358643Abstract: An apparatus is provided which comprises: a memory array; first logic to detect whether first and second word-lines (WL) for a row of the memory array are active; and second logic to deactivate one of the first and second WLs such that one of the first and second WLs is active for the row.Type: ApplicationFiled: June 4, 2015Publication date: December 8, 2016Inventors: Pramrod Kolar, Wei-Hsiang Ma, Gunjan H. Pandya