Patents by Inventor Wei Hsu

Wei Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250038641
    Abstract: A voltage regulator with diode retention is shown, which includes an input terminal receiving a supply voltage, an output terminal providing a regulated voltage, and a main circuit coupled between the input terminal and the output terminal. In a normal mode, the main circuit transforms the supply voltage to a first voltage as the regulated voltage. In a sleep mode, the voltage regulator provides a diode connected between the input terminal and the output terminal of the voltage regulator, to generate a second voltage as the regulated voltage. The second voltage is lower than the first voltage.
    Type: Application
    Filed: July 5, 2024
    Publication date: January 30, 2025
    Inventors: Chung-Wei HSU, Wei-Hsin TSENG
  • Publication number: 20250040334
    Abstract: The present disclosure provides a photoelectric device module and a manufacturing method thereof. The photoelectric device module includes a circuit module and a photoelectric conversion module. The circuit module includes a first electrode. The photoelectric conversion module is disposed on the circuit module, in which the photoelectric conversion module includes a second electrode, a photoactive layer, a light-transmitting electrode, and a light-transmitting substrate. The second electrode is electrically connected to the first electrode. The photoactive layer is disposed on the second electrode. The light-transmitting electrode is disposed on the photoactive layer. The light-transmitting substrate is disposed on the light-transmitting electrode.
    Type: Application
    Filed: July 25, 2024
    Publication date: January 30, 2025
    Inventors: Yi-Ming CHANG, Cheng-En TSAI, Chung-Wei HSU
  • Publication number: 20250035718
    Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a reference layer on the pinned layer, a barrier layer on the reference layer, and a free layer on the barrier layer. Preferably, the free layer and the barrier layer have same width and the barrier layer and the reference layer have different widths.
    Type: Application
    Filed: October 15, 2024
    Publication date: January 30, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Hui-Lin Wang, Chen -Yi Weng, Che-Wei Chang, Si-Han Tsai, Ching-Hua Hsu, Jing-Yin Jhang, Yu-Ping Wang
  • Publication number: 20250036977
    Abstract: An electronic device is configured to execute instructions: compiling a first AI model and second AI model(s) to a first compiled file and second compiled file(s), respectively, wherein the first compiled file comprises a first data set and a first command set, and the second compiled file(s) comprises second data set(s) and second command set(s); generating light version file(s) for the AI model(s), wherein the light version file(s) comprises the second command set(s) and data patch(es); storing the first compiled file and the light version file(s) to a storage device; loading the first compiled file from the storage device to a memory; loading the light version file(s) from the storage device to the memory; generating the second data set(s) according to the first data set and the data patch(es); and executing the second AI model(s) according to the generated second data set(s) and the second command set(s) in the memory.
    Type: Application
    Filed: June 23, 2024
    Publication date: January 30, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chia-Wei Hsu, Yu-Lung Lu, Yen-Ting Chiang, Chih-wei Chen, Yi-Cheng Lu, Jia-Sian Hong, Kuan-Yu Chen, Pei-Kuei Tsung, Hua Wu
  • Publication number: 20250040233
    Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.
    Type: Application
    Filed: October 14, 2024
    Publication date: January 30, 2025
    Inventors: Kuo-Cheng CHING, Lung-Kun Chu, Mao-Lin Huang, Chung-Wei Hsu
  • Publication number: 20250039356
    Abstract: A video coding system that uses multiple models to predict chroma samples is provided. The video coding system receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coding system derives multiple prediction linear models based on luma and chroma samples neighboring the current block. The video coding system constructs a composite linear model based on the multiple prediction linear models. The video coding system applies the composite linear model to incoming or reconstructed luma samples of the current block to generate a chroma predictor of the current block. The video coding system uses the chroma predictor to reconstruct chroma samples of the current block or to encode the current block.
    Type: Application
    Filed: December 29, 2022
    Publication date: January 30, 2025
    Inventors: Chia-Ming TSAI, Chun-Chia CHEN, Yu-Ling HSIAO, Man-Shu CHIANG, Chih-Wei HSU, Olena CHUBACH, Tzu-Der CHUANG, Ching-Yeh CHEN, Yu-Wen HUANG
  • Publication number: 20250038960
    Abstract: An example may involve determining that a first proxy server is to share security credentials with a set of one or more proxy servers, wherein the set of one or more proxy servers is associated with the security credentials, and wherein the set of one or more proxy servers includes a second proxy server; transmitting, to the second proxy server, a request for the first proxy server to have access to the security credentials; and receiving, from the second proxy server, a credential key in an encrypted form, wherein the credential key is configured to decrypt the security credentials.
    Type: Application
    Filed: July 24, 2023
    Publication date: January 30, 2025
    Inventors: Jiayin Song, Matis Granger, Shu-Wei Hsu
  • Publication number: 20250038106
    Abstract: A bond structure is provided. The bond structure includes a seed layer and a conductive structure. The conductive structure includes a via portion over the seed layer and a plurality of wires protruding from the via portion.
    Type: Application
    Filed: July 28, 2023
    Publication date: January 30, 2025
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chun-Wei CHIANG, Yung-Sheng LIN, I-Ting LIN, Ping-Hung HSIEH, Chih-Yuan HSU
  • Publication number: 20250040213
    Abstract: A semiconductor structure includes a source/drain feature in the semiconductor layer. The semiconductor structure includes a dielectric layer over the source/drain feature. The semiconductor structure includes a silicide layer over the source/drain feature. The semiconductor structure includes a barrier layer over the silicide layer. The semiconductor structure includes a seed layer over the barrier layer. The semiconductor structure includes a metal layer between a sidewall of the seed layer and a sidewall of the dielectric layer, a sidewall of each of the silicide layer, the barrier layer, and the metal layer directly contacting the sidewall of the dielectric layer. The semiconductor structure includes a source/drain contact over the seed layer.
    Type: Application
    Filed: July 27, 2023
    Publication date: January 30, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: Yi-Hsiang Chao, Peng-Hao Hsu, Yu-Shiuan Wang, Chi-Yuan Chen, Yu-Hsiang Liao, Chun-Hsien Huang, Hung-Chang Hsu, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 12209664
    Abstract: An electrically and thermally conductive gasket includes a resilient core including a plurality of sides, a heat spreader disposed along at least two sides of the plurality of sides of the resilient core, and an electrically conductive layer disposed along and/or covering at least a portion of the heat spreader, such that the portion of the heat spreader is between the resilient core and the electrically conductive layer. The gasket is positionable and/or compressible between first and second surfaces to thereby define an electrically conductive path and a thermally conductive path between the first and second surfaces.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: January 28, 2025
    Assignee: Laird Technologies (Shenzhen) Ltd.
    Inventors: Yi-Shen Lin, Min-Wei Hsu, Tsang-I Tsai
  • Patent number: 12210811
    Abstract: A method performed by at least one processor includes the following steps: generating a layout of an integrated circuit (IC), the layout comprising a cell and a layout context in a vicinity of the cell; receiving from a library a set of context groups and a set of timing tables, wherein each of the context groups is associated with one of the set of timing tables; determining a representative context group for the cell through comparing the layout context of the cell with the set of context groups; and performing a timing analysis on the layout according to a representative timing table associated with the representative context group for the cell.
    Type: Grant
    Filed: November 23, 2023
    Date of Patent: January 28, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Zhe-Wei Jiang, Jerry Chang Jui Kao, Sung-Yen Yeh, Li Chung Hsu
  • Patent number: 12211188
    Abstract: Image dewarping includes capturing a source image from a camera, selecting an input row of pixels from the source image, if the input row of pixels comprises a plurality of input pixels in a region of interest in the source image, storing the plurality of input pixels to a memory to generate an input segment of pixels, when a plurality of pixels required to generate an output row of pixels are all stored in the memory, reading from the memory the plurality of pixels corresponding to the output row of pixels, and performing coordinate transformation on the plurality of pixels to generate the output row of pixels, and when coordinate transformation has been completed on the plurality of pixels, releasing from the memory an input segment of pixels of the plurality of input segments of pixels that does not correspond to other output rows of pixels.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: January 28, 2025
    Assignee: WELTREND SEMICONDUCTOR INC.
    Inventors: Hsuan-Ying Chen, Hung-Chih Chiang, Ta Hsien, Te-Wei Hsu, Meng-Che Tsai
  • Publication number: 20250026720
    Abstract: A method of manufacturing triacetonamine includes (a) introducing an acetone and an ammonia into a first reactor in the presence of a first acidic catalyst to form an acetonin; (b) introducing the acetonin and water into a second reactor in the presence of a second acidic catalyst to form a triacetonamine and side products, wherein the side products include diacetone alcohol, diacetone amine, mesityl oxide, 2,2,4,6-tetramethyl-2,3-dihydropyridine, or a combination thereof; (c) separating the triacetonamine and the side products by distillation under reduced pressure; (d) introducing the side products and water into a third reactor to heat and crack the side products in the presence of an amphiphilic catalyst to form acetone; and (e) introducing the acetone obtained from step (d) into the first reactor.
    Type: Application
    Filed: June 28, 2024
    Publication date: January 23, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jyun-Wei HONG, Chien-Wei HSU
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Patent number: 12206005
    Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDICTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20250022789
    Abstract: A package substrate and a method of fabrication thereof including stress buffer layers. Each stress buffer layer may be vertically spaced from and at least partially overlap with a corresponding bonding pad of the package substrate. The stress buffer pads may provide structural reinforcement to distribute tensile stress on the package substrate and inhibit warpage and crack formation in the package substrate. The stress buffer pads may additionally improve an insertion loss characteristic of the package substrate. Accordingly, semiconductor package performance, reliability and yields may be improved.
    Type: Application
    Filed: July 31, 2024
    Publication date: January 16, 2025
    Inventors: Chung-Hsin Chen, Chi Wei Hsu, Sih Han Chen, Yi Chung Chen
  • Publication number: 20250024072
    Abstract: A method and apparatus for video coding system that uses intra prediction based on cross-colour linear model are disclosed. According to the method, model parameters for a first-colour predictor model are determined and the first-colour predictor model provides a predicted first-colour pixel value according to a combination of at least two corresponding reconstructed second-colour pixel values. According to another method, the first-colour predictor model provides a predicted first-colour pixel value based on a second degree model or higher of one or more corresponding reconstructed second-colour pixel values. First-colour predictors for the current first-colour block are determined according to the first-colour prediction model. The input data are then encoded at the encoder side or decoded at the decoder side using the first-colour predictors.
    Type: Application
    Filed: October 26, 2022
    Publication date: January 16, 2025
    Inventors: Olena CHUBACH, Ching-Yeh CHEN, Tzu-Der CHUANG, Chun-Chia CHEN, Man-Shu CHIANG, Chia-Ming TSAI, Yu-Ling HSIAO, Chih-Wei HSU, Yu-Wen HUANG
  • Publication number: 20250022810
    Abstract: A package substrate and a method of fabrication thereof including stress buffer layers. Each stress buffer layer may be vertically spaced from and at least partially overlap with a corresponding bonding pad of the package substrate. The stress buffer pads may provide structural reinforcement to distribute tensile stress on the package substrate and inhibit warpage and crack formation in the package substrate. Accordingly, semiconductor package reliability and yields may be improved.
    Type: Application
    Filed: July 10, 2023
    Publication date: January 16, 2025
    Inventors: Chung-Hsin Chen, Chi Wei Hsu, Sih Han Chen, Yi Chung Chen
  • Publication number: 20250020209
    Abstract: An electrically and thermally conductive gasket includes a resilient core including a plurality of sides, a heat spreader disposed along at least two sides of the plurality of sides of the resilient core, and an electrically conductive layer disposed along and/or covering at least a portion of the heat spreader, such that the portion of the heat spreader is between the resilient core and the electrically conductive layer. The gasket is positionable and/or compressible between first and second surfaces to thereby define an electrically conductive path and a thermally conductive path between the first and second surfaces.
    Type: Application
    Filed: October 1, 2024
    Publication date: January 16, 2025
    Inventors: Yi-Shen LIN, Min-Wei HSU, Tsang-I TSAI
  • Publication number: 20250023604
    Abstract: The application discloses a device and method for beamforming. The beamforming method comprises: sending a null data packet announcement (NDPA) frame from a beamformer to a pseudo user and a target user to indicate the target user to prepare for channel estimation; sending a null data packet (NDP) from the beamformer to the target user and performing channel estimation by the target user based on the NDP to determine channel state information; sending a beamforming report poll (BRP) trigger frame from the beamformer to the target user to trigger the target user to feed back channel state information; and sending from the target user a beamforming report to the beamformer, wherein the beamforming report including the channel state information.
    Type: Application
    Filed: June 14, 2024
    Publication date: January 16, 2025
    Inventors: Li-Chieh CHEN, Cheng-En HSIEH, Wei-Hsu CHEN, Ming-Hsiang TSENG, Kang-Li WU