Patents by Inventor Wei Hsu
Wei Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250148593Abstract: An analysis method for optimizing number and position of screws used in long bone (fracture fixation) surgery, including the following steps. Perform a CT scan on a surgical patient to obtain a medical image to build a long bone 3D model. Analyze an X-ray image to obtain a long bone fracture condition and a bone quality condition. Select a bone plate 3D model from the model database. Import the bone plate 3D model into the long bone 3D model and set an initial fixation position of the bone plate 3D model. Instruct the first artificial intelligence to comprehensively analyze the conditions to automatically select alternative solutions in the model database. Then, use a computer-aided analysis system to analyze the stress distribution of the alternative solutions, and a first preferred solution is obtained through simulating analysis, thereby excluding incorrect or ineffective surgical plans to reduce the analysis time and patient wait time and increasing the surgery success rate.Type: ApplicationFiled: October 25, 2024Publication date: May 8, 2025Applicant: NATIONAL FORMOSA UNIVERSITYInventors: Shou-I Chen, Yu-Hsu Chen, Shau-Huai Fu, Chih-Min Yao, Wei-Sheng Hong, Mu-Kuang He, Fan-Jun Xie
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Publication number: 20250150601Abstract: A video coding system that reorders prediction candidates is provided. A video coder receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coder identifies possible candidate prediction positions. The video coder computes a cost for each of the identified possible candidate prediction positions. The video coder assigns, based on the computed costs, a reordered index to each of N lowest cost candidate prediction positions from the identified possible candidate prediction positions. The video coder selects a candidate prediction position using the assigned reordered indices, wherein the selection is signaled in or parsed from the bitstream. The video coder encodes or decodes the current block by using the selected candidate prediction position.Type: ApplicationFiled: August 15, 2022Publication date: May 8, 2025Inventors: Chih-Yao CHIU, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG, Yu-Wen HUANG
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Publication number: 20250149392Abstract: A package substrate includes a core layer, at least one functional component, at least one spacer, a filler, a first and a second build-up structures. The core layer has at least one opening and multiple conductive through vias. The functional component is disposed in the openings. The spacer is disposed on the functional component. The filler is filled in the opening, covering the functional component and spacer, and completely filling the gap between the opening, the functional component and the spacer. The first build-up structure is disposed on a first surface of the core layer and a third surface of the filler, and electrically connected to the functional component and the conductive through vias. The second build-up structure is disposed on a second surface of the core layer and a fourth surface of the filler, contacts the spacer and electrically connected to the conductive through vias.Type: ApplicationFiled: December 26, 2023Publication date: May 8, 2025Applicant: Unimicron Technology Corp.Inventors: Chia Ching Wang, Chien-Chou Chen, Hsuan Ming Hsu, Ho-Shing Lee, Yunn-Tzu Yu, Yao Yu Chiang, Po-Wei Chen, Wei-Ti Lin, Wen Chi Chang
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Publication number: 20250148336Abstract: It is an objective to provide an arrangement for initialising at least one qubit to a thermal state. According to an embodiment, an arrangement for initialising at least one qubit to a thermal state comprises: at least one qubit; a thermal bath structure selectively couplable to the at least one qubit, wherein the selective coupling is controllable using at least one coupling control signal, and wherein an effective temperature of the thermal bath structure is controllable via a temperature control signal; and a control unit configured to: set the effective temperature of the thermal bath structure to a target effective temperature via the temperature control signal; and initialise the at least one qubit to a thermal state by coupling the at least one qubit to the thermal bath structure in the target effective temperature using the at least one coupling control signal.Type: ApplicationFiled: February 16, 2022Publication date: May 8, 2025Inventors: Hao HSU, Hermanni HEIMONEN, Jami RÖNKKÖ, Vasilii SEVRIUK, Wei LIU
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Publication number: 20250150600Abstract: A method that reorders partitioning candidates or motion vectors based on template matching costs for geometric prediction mode (GPM) is provided. A video coder receives data to be encoded or decoded as a current block of a current picture of a video. The current block is partitioned into first and second partitions by a bisecting line defined by an angle-distance pair. The video coder identifies a list of candidate prediction modes for coding the first and second partitions. The video coder computes a template matching (TM) cost for each candidate prediction mode in the list. The video coder receives or signals a selection of a candidate prediction mode based on an index that is assigned to the selected candidate prediction mode based on the computed TM costs. The video coder reconstructs the current block by using the selected candidate prediction mode to predict the first and second partitions.Type: ApplicationFiled: August 15, 2022Publication date: May 8, 2025Inventors: Chih-Yao CHIU, Chih-Hsuan LO, Chun-Chia CHEN, Chih-Wei HSU, Ching-Yeh CHEN, Tzu-Der CHUANG
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Patent number: 12294030Abstract: A semiconductor structure includes a first pair of source/drain features (S/D), a first stack of channel layers connected to the first pair of S/D, a second pair of S/D, and a second stack of channel layers connected to the second pair of S/D. The first pair of S/D each include a first epitaxial layer having a first dopant, a second epitaxial layer having a second dopant and disposed over the first epitaxial layer and connected to the first stack of channel layers, and a third epitaxial layer having a third dopant and disposed over the second epitaxial layer. The second pair of S/D each include a fourth epitaxial layer having a fourth dopant and connected to the second stack of channel layers, and a fifth epitaxial layer having a fifth dopant and disposed over the fourth epitaxial layer. The first dopant through the fourth dopant are of different species.Type: GrantFiled: May 24, 2024Date of Patent: May 6, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Hao Lin, Chih-Hsuan Chen, Chia-Hao Pao, Chih-Chuan Yang, Chih-Yu Hsu, Hsin-Wen Su, Chia-Wei Chen
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Patent number: 12294037Abstract: A light-emitting diode chip includes a substrate. The substrate has a side surface configured as a serrated surface, which includes a plurality of laser inscribed features disposed along a thickness direction of the substrate and spaced apart from each other. A method for manufacturing the light-emitting diode chip is also disclosed herein.Type: GrantFiled: October 12, 2021Date of Patent: May 6, 2025Assignee: QUANZHOU SAN'AN SEMICONDUCTOR TECHNOLOGY CO., LTD.Inventors: Gong Chen, Su-Hui Lin, Sheng-Hsien Hsu, Kang-Wei Peng, Ling-Yuan Hong, Minyou He, Chia-Hung Chang
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Publication number: 20250137072Abstract: This application relates to stem cell biology and regenerative medicine. Disclosed herein are methods for isolation of skeletal stem cells, related methods, related compositions, related products, and related uses.Type: ApplicationFiled: February 16, 2023Publication date: May 1, 2025Applicants: ADA Forsyth Institute, Inc., University of RochesterInventors: Wei Hsu, Zhirui Jiang
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Publication number: 20250138050Abstract: A vertical probe includes opposite first and third sides, and opposite second and fourth sides. The third and fourth sides extend in a planar manner from a body to a tip portion. The first and second sides include first and second upper plane segments at the body, first and second transition segments at the tip portion, and first and second lower plane segments closer to the third and fourth sides than the first and second upper plane segments are, respectively. The first and second transition segments gradually approach the third and fourth sides as they extend from the first and second upper plane segments to the first and second lower plane segments. The first transition and lower plane segments are realized by laser processing. The vertical probe can contact small conductive contacts with good current resistance, structural strength, lifespan, and processing accuracy. When applied to a probe head, breaking or shifting position of the tip portion due to vertical movement can be avoided.Type: ApplicationFiled: October 28, 2024Publication date: May 1, 2025Applicant: MPI CORPORATIONInventors: CHIN-YI LIN, HSIEN-TA HSU, CHE-WEI LIN, CHIH-MING HUANG
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Publication number: 20250142728Abstract: Provided is a coil carrier board, including a base coil layer, a conductive layer stacked on and bonded to the base coil layer, at least one build-up coil layer stacked on and bonded to the conductive layer, and an opening connecting the base coil layer, the conductive layer and the build-up coil layer. The coil carrier board has thick copper, fine line spacing and appropriate rigidity by means of the build-up circuit process and the structural design of the insulating layer of a photosensitive dielectric material bonded with a thermosetting dielectric material. Accordingly, the high current-carrying efficiency of the coil carrier board is enhanced, and the overall structure of the coil carrier board has better flatness, rigidity and high interlayer alignment accuracy, thereby facilitating miniaturization and automated assembly production.Type: ApplicationFiled: October 25, 2024Publication date: May 1, 2025Applicant: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Che-Wei HSU, Wen-Hung HU, Shih-Ping HSU
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Publication number: 20250142943Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. The semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. The semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.Type: ApplicationFiled: January 6, 2025Publication date: May 1, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng CHIANG, Chung-Wei HSU, Lung-Kun CHU, Jia-Ni YU, Chih-Hao WANG, Mao-Lin HUANG
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Patent number: 12288695Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.Type: GrantFiled: March 25, 2022Date of Patent: April 29, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Mao-Lin Huang, Lung-Kun Chu, Jia-Ni Yu, Chun-Fu Lu, Chih-Hao Wang
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Patent number: 12290004Abstract: A semiconductor device includes an array region defined on a substrate, a ring of dummy pattern surrounding the array region, and a gap between the array region and the ring of dummy pattern. Preferably, the ring of dummy pattern further includes a ring of magnetic tunneling junction (MTJ) pattern surrounding the array region and a ring of metal interconnect pattern overlapping the ring of MTJ and surrounding the array region.Type: GrantFiled: May 26, 2024Date of Patent: April 29, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chih-Wei Kuo, Chia-Chang Hsu
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Patent number: 12287387Abstract: A method of using non-contrast magnetic resonance angiography (NC-MRA) to generate pelvic veins images and measure rate of blood flow includes the ordered steps of: (a) performing a non-contrast magnetic resonance scan in cooperation with an electrocardiogram monitor and a respiration monitor; (b) obtaining two-dimensional images of kidney veins, lower cavity veins, common iliac veins, and external iliac veins using use balanced turbo field echo wave sequence; (c) obtaining three-dimensional images of common cardinal veins of the abdominal cavity using fast spin-echo short tau inversion recovery wave sequence and using sample signals from the electrocardiogram monitor during myocardial contractility; and (d) using quantification phase-contrast analysis to measure blood flowing through the transverse sections of the veins in a two-dimensional scan.Type: GrantFiled: September 1, 2022Date of Patent: April 29, 2025Assignee: Chang Gung Memorial Hospital, ChiayiInventors: Chien-Wei Chen, Yao-Kuang Huang, Chung-Yuan Lee, Yeh-Giin Ngo, Yin-Chen Hsu
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Publication number: 20250132664Abstract: A power supply system with power factor correction, includes: an AC rectifier, a power factor correction (PFC) conversion circuit, an asymmetric half-bridge (AHB) flyback converter and a communication protocol power delivery (PD) interface. When a power level of an adapter output power is lower than a power threshold, and a converted voltage of a converted power is higher than a first voltage threshold, the communication protocol PD interface generates a disable signal to disable a PFC conversion of the PFC conversion circuit, when the PFC conversion is disabled, the PFC conversion circuit operates a bypass coupling operation, as thus, the converted voltage is equal to a rectified voltage of a rectified power.Type: ApplicationFiled: January 10, 2024Publication date: April 24, 2025Inventors: Wei-Hsu Chang, Kun-Yu Lin, Jyun-Che Ho
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Publication number: 20250133180Abstract: A teleprompter includes a connecting bracket, a prompting optical mechanism, a transferring board, and a supporting seat. The connecting bracket is used to support a monitor assembly. The prompting optical mechanism includes a main housing, a front frame, a rear frame, and a splitter. The transferring board is detachably connected to the rear frame. The transferring board has a photography opening. The supporting seat has an assembly board, and a horizontal carrier. The horizontal carrier is connected to a top end of the assembly board. The assembly board is connected to one side of the connecting bracket, and can be adjusted to different positions of the connecting bracket. Therefore, the horizontal carrier can be adjusted to different heights corresponding with the photography opening of the transferring board.Type: ApplicationFiled: February 21, 2024Publication date: April 24, 2025Inventors: YU-CHENG CHANG, CHIN-WEI HSU, SHANG-FU WANG, CHIA-HSIN TSAI
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Publication number: 20250133716Abstract: A method according to the present disclosure includes receiving a structure. The structure includes a substrate, a first fin-shaped structure, a second fin-shaped structure, and a third fin-shaped structure disposed over the substrate, and a first isolation feature between the first fin-shaped structure and the second fin-shaped structure and a second isolation feature between the second fin-shaped structure and the third fin-shaped structure. The method further includes depositing a first dielectric layer over the first isolation feature and the second isolation feature, depositing a second dielectric layer over the first dielectric layer and the first isolation feature, but not over the second isolation feature, performing a first selective etching process to the first dielectric layer and the second dielectric layer, and performing a second selective etching process to the first dielectric layer over the second isolation feature.Type: ApplicationFiled: December 23, 2024Publication date: April 24, 2025Inventors: Wen-Chun Keng, Kuo-Hsiu Hsu, Chih-Chuan Yang, Lien Jung Hung, Ping-Wei Wang
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Patent number: 12281787Abstract: An adapter includes an enclosure, a circuit module, a shielding element, a control module, a backlight module, and a masking element. The circuit module and the control module are arranged in the accommodating slot of the enclosure. The shielding element covers the circuit module and the control module is connected to the circuit module. The backlight module is located outside the shielding element and is connected to the control module. The wiring terminal of the backlight module is connected to the control module. The light-emitting area of the backlight module and the masking element are corresponds to the transparent area of the side surface of the enclosure. The control module controls the backlight module to cause the light-emitting area to emit light to irradiate the masking element, so that part of the light penetrates the enclosure through the transparent area and forms an illuminated icon.Type: GrantFiled: January 5, 2024Date of Patent: April 22, 2025Assignee: Chicony Power Technology Co., Ltd.Inventors: Tsai-Liang Hsu, Hung-Yueh Hsiao, Hsuan-Wei Ho
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Patent number: 12282247Abstract: A detection device includes a substrate, a light source, a detection module, and a heat dissipation module. The substrate includes a first base plate, a second base plate, and at least one connecting portion connecting the first base plate to the second base plate. The light source is disposed on the first base plate. The detection module is disposed on the second base plate. The first base plate has a first surface towards the at least one connecting portion, and the at least one connecting portion has a second surface towards the first base plate. The second surface is connected to a portion of the first surface. The heat dissipation module is disposed on the at least one connecting portion and/or the second base plate, and the influence of heat on proper operation of the detection device is thus prevented.Type: GrantFiled: June 1, 2022Date of Patent: April 22, 2025Assignees: HONGFUJIN PRECISION ELECTRONICS (ZHENGZHOU) CO., LTD., Henan Fuchi Technology Co., Ltd.Inventors: Hsin-Ta Lin, Chia-Wei Hsu
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Patent number: 12282723Abstract: A method including: providing a design data of an integrated circuit (IC), the design data comprising a first cell; identifying a first conductive line in the first cell as a critical internal net of the first cell, wherein the first conductive line is electrically connected between an input terminal of the first cell and an output terminal of the first cell; providing a library of the first cell, wherein the library includes a table of timing or power parameters of the first cell based on a multidimensional input set associated with the critical internal net; updating the design data by determining a timing or power value of the first cell based on the table; performing a timing analysis on the updated design data; and forming a photomask based on the updated design data.Type: GrantFiled: February 15, 2022Date of Patent: April 22, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shi-Han Zhang, You-Cheng Lai, Jerry Chang Jui Kao, Pei-Wei Liao, Shang-Chih Hsieh, Meng-Kai Hsu, Chih-Wei Chang