Patents by Inventor Wei Hsu
Wei Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250118695Abstract: A package component includes an insulating substrate, a semiconductor structure, a first conductive line and a conductive pad. The semiconductor structure is disposed in the insulating substrate and separated from the insulating substrate. The first conductive line is disposed on a first side of the insulating substrate. The conductive pad is disposed on a first side of the semiconductor structure. The first conductive line and the conductive pad include a same material. A surface roughness of the conductive pad is greater than a surface roughness of the first conductive line.Type: ApplicationFiled: October 10, 2023Publication date: April 10, 2025Inventors: MING-WEI PENG, HUNG EN HSU, KUO-CHING HSU
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Publication number: 20250120123Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a gate dielectric layer disposed over a substrate, a gate electrode layer disposed over the gate dielectric layer, and a first gate spacer disposed adjacent the gate dielectric layer, wherein the first gate spacer comprises an inner surface facing the gate dielectric layer and an outer surface opposite the inner surface, and the first gate spacer includes an oxygen concentration that decreases from the inner surface towards the outer surface of the first gate spacer.Type: ApplicationFiled: January 24, 2024Publication date: April 10, 2025Inventors: Chun-Fu LU, Lung-Kun CHU, Jia-Ni YU, Chung-Wei HSU, Shih-Hao LAI, Kuo-Cheng CHIANG, Chih-Hao WANG
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Publication number: 20250120166Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.Type: ApplicationFiled: December 16, 2024Publication date: April 10, 2025Inventors: Chung-Wei Hsu, Kuo-Cheng Chiang, Kuan-Lun Cheng, Hou-Yu Chen, Ching-Wei Tsai, Chih-Hao Wang, Lung-Kun Chu, Mao-Lin Huang, Jia-Ni Yu
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Patent number: 12274180Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.Type: GrantFiled: March 17, 2023Date of Patent: April 8, 2025Assignee: UNITED MICROELECTRONICS CORP.Inventors: Hui-Lin Wang, Chen-Yi Weng, Si-Han Tsai, Che-Wei Chang, Po-Kai Hsu, Jing-Yin Jhang, Yu-Ping Wang, Ju-Chun Fan, Ching-Hua Hsu, Yi-Yu Lin, Hung-Yueh Chen
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Patent number: 12272557Abstract: In an embodiment, a method includes: depositing a gate dielectric layer on a first fin and a second fin, the first fin and the second fin extending away from a substrate in a first direction, a distance between the first fin and the second fin decreasing along the first direction; depositing a sacrificial layer on the gate dielectric layer by exposing the gate dielectric layer to a self-limiting source precursor and a self-reacting source precursor, the self-limiting source precursor reacting to form an initial layer of a material of the sacrificial layer, the self-reacting source precursor reacting to form a main layer of the material of the sacrificial layer; annealing the gate dielectric layer while the sacrificial layer covers the gate dielectric layer; after annealing the gate dielectric layer, removing the sacrificial layer; and after removing the sacrificial layer, forming a gate electrode layer on the gate dielectric layer.Type: GrantFiled: August 1, 2023Date of Patent: April 8, 2025Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kuei-Lun Lin, Chia-Wei Hsu, Xiong-Fei Yu, Chi On Chui, Chih-Yu Hsu, Jian-Hao Chen
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Patent number: 12273035Abstract: A conversion control circuit controls plural stackable sub-converters which are coupled in parallel to generate an output power to a load, the conversion control circuit includes: a current sharing terminal, wherein a current sharing signal is configured to be connected to the current sharing terminals, in parallel, of the plurality of the conversion control circuits; and a current sharing circuit, configured to generate or receive the current sharing signal which is generated according to an output current of the output power; wherein the conversion control circuit adjusts the power stage circuit according to the current sharing signal for current sharing among the plural stackable sub-converters.Type: GrantFiled: March 21, 2023Date of Patent: April 8, 2025Assignee: Richtek Technology CorporationInventors: Ta-Yung Yang, Wei-Hsu Chang, Kuo-Chi Liu, Chao-Chi Chen
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Patent number: 12272653Abstract: A semiconductor packaging substrate is provided, which includes a build-up circuit structure, at least one fiducial marker structure, and an insulating protective layer. The fiducial marker structure includes a fiducial marker and a second insulating layer covering the fiducial marker. The second insulating layer is made of a transparent insulation material, so that the fiducial marker inside the second insulating layer can be seen through a CCD lens or tool maker microscope for alignment so as to easily create a smaller see-through area and the process parameters can be easily controlled. Besides, the disclosure further provides a manufacturing method for the semiconductor packaging substrate.Type: GrantFiled: November 17, 2022Date of Patent: April 8, 2025Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.Inventors: Chao-Tsung Tseng, Che-Wei Hsu
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Patent number: 12272751Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.Type: GrantFiled: February 13, 2023Date of Patent: April 8, 2025Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Hsing Hsu, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Sai-Hooi Yeong
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Patent number: 12270709Abstract: An infrared sensor uses an infrared lens with infrared filtering and focusing functions. Thus, an infrared filter can be omitted to reduce the costs and volume. In addition, a getter on the inside of a metal cover of the infrared sensor can be activated when the metal cover is soldered to the substrate of the infrared sensor. Therefore, the packaging process of the infrared sensor can be simplified.Type: GrantFiled: May 25, 2021Date of Patent: April 8, 2025Assignee: TXC CORPORATIONInventors: Tzong-Sheng Lee, Jen-Wei Luo, Chia-Hao Weng, Chun-Chi Lin, Ting-Chun Hsu, Hui-Jou Yu, Yi-Hung Lin, Sung-Hung Lin
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Publication number: 20250110172Abstract: A semiconductor package includes an array of through-substrate-via (TSV) structures comprising a number (O) of TSV structures, wherein the array comprises a number (M) of active TSV structures; a number (N) of contact structures, the contact structures comprising a plurality of pairs configured to receive an input test signal and provide an output test signal, respectively; and a plurality of binary-tree branches, each of the plurality of binary-tree branches electrically coupling a first one of the active TSV structures to a second one of the active TSV structures and a third one of the active TSV structures.Type: ApplicationFiled: October 2, 2023Publication date: April 3, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Chih Hsu, Jui-Cheng Huang, Mu Wei Lee, Wei-Tao Shaw
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Publication number: 20250110307Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: ApplicationFiled: December 12, 2024Publication date: April 3, 2025Inventors: Chao-Chang HU, Chih-Wei WENG, Chia-Che WU, Chien-Yu KAO, Hsiao-Hsin HU, He-Ling CHANG, Chao-Hsi WANG, Chen-Hsien FAN, Che-Wei CHANG, Mao-Gen JIAN, Sung-Mao TSAI, Wei-Jhe SHEN, Yung-Ping YANG, Sin-Hong LIN, Tzu-Yu CHANG, Sin-Jhong SONG, Shang-Yu HSU, Meng-Ting LIN, Shih-Wei HUNG, Yu-Huai LIAO, Mao-Kuo HSU, Hsueh-Ju LU, Ching-Chieh HUANG, Chih-Wen CHIANG, Yu-Chiao LO, Ying-Jen WANG, Shu-Shan CHEN, Che-Hsiang CHIU
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Publication number: 20250108114Abstract: Provided is an isolated nucleic acid molecule comprising a NKp30 transmembrane domain, and a chimeric antigen receptor comprising the same. The isolated nucleic acid molecule comprising a NKp30 transmembrane domain comprises nucleic acid sequences encoding (a) an extracellular antigen binding domain, comprising a heavy chain variable region; (b) a hinge domain; (c) a NKp30 transmembrane domain; and (d) a NKp30 cytoplasmic domain. By introducing nucleic acid sequences of the NKp30 transmembrane domain and the NKp30 cytoplasmic domain in combination with the extracellular antigen binding domain into a T cell, the resulting CAR-T cell is a multi-chain CAR-T cell with a NKp30 receptor complex. Consequently, the resulting CAR-T cell forms stable immune synapses with cancer cells and exhibits excellent cytotoxicity against cancer cells.Type: ApplicationFiled: September 26, 2024Publication date: April 3, 2025Inventors: Felix HSU, Wei-Chi LIN, Wen-Ting WU, Chen-Lung LIN
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Publication number: 20250113028Abstract: A method and apparatus for video coding are disclosed for the encoder side and the decoder side. According to the method for the decoder side, encoded data associated with a current block is received. A pseudo GPM in a target GPM group for the current block is determined. The current block is divided into one or more subblocks. Assigned MVs (Motion Vectors) of each subblock are determined according to the pseudo GPM. A cost for each GPM in the target GPM group is determined according to decoded data. A selected GPM is determined based on a mode syntax and a reordered target GPM group corresponding to the target GPM group reordered according to the costs, wherein the pseudo GPM is allowed to be different from the selected GPM. The encoded data is decoded using information comprising the selected GPM.Type: ApplicationFiled: January 13, 2023Publication date: April 3, 2025Inventors: Tzu-Der CHUANG, Ching-Yeh CHEN, Chih-Wei HSU
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Publication number: 20250111157Abstract: Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for analyzing embedding spaces using large language models. In one aspect, a method performed by one or more computers for analyzing a target embedding space using a neural network configured to perform a set of machine learning tasks is described. The method includes: obtaining, for each of one or more entities, a respective domain embedding representing the entity in the target embedding space; receiving a text prompt including a sequence of input tokens describing a particular machine learning task in the set to be performed on the one or more entities; preparing, for the neural network, an input sequence including each input token in the text prompt and each domain embedding; and processing the input sequence, using the neural network, to generate a sequence of output tokens describing a result of the particular machine learning task.Type: ApplicationFiled: September 27, 2024Publication date: April 3, 2025Inventors: Guy Tennenholtz, Yinlam Chow, Chih-wei Hsu, Jihwan Jeong, Lior Shani, Deepak Ramachandran, Martin Mirolyubov Mladenov, Craig Edgar Boutilier
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Publication number: 20250112087Abstract: A method for fabricating an integrated circuit device is provided. The method includes depositing a first dielectric layer; depositing a second dielectric layer over the first dielectric layer; etching a trench opening in the second dielectric layer, wherein the trench opening exposes a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer, the first sidewall of the second dielectric layer extends substantially along a first direction, and the second sidewall of the second dielectric layer extends substantially along a second direction different from the first direction in a top view; forming a via etch stop layer on the first sidewall of the second dielectric layer, wherein the second sidewall of the second dielectric layer is free from coverage by the via etch stop layer; forming a conductive line in the trench opening; and forming a conductive via over the conductive line.Type: ApplicationFiled: October 3, 2023Publication date: April 3, 2025Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hwei-Jay CHU, Hsi-Wen TIEN, Wei-Hao LIAO, Yu-Teng DAI, Hsin-Chieh YAO, Tzu-Hui WEI, Chih Wei LU, Chan-Yu LIAO, Li-Ling SU, Chia-Wei SU, Yung-Hsu WU, Hsin-Ping CHEN
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Patent number: 12263297Abstract: A nebulizer includes a main body (1), a spraying head (2) and an engagement structure (4). The main body (1) includes a body (11). The spraying head (2) includes a spraying seat (21) assembled to the body (11). The engagement structure (4) includes a notch (41) formed on one of the body (11) and the spraying seat (21), a T-shaped trench (42) formed on an inner wall of the notch (41), an engaging trench (43) formed on another one of the body (11) and the spraying seat (21), and a movable member (44) received in the notch (41). The movable member (44) is extended with a handle (441) exposed from the notch (41), a T-shaped block (442) slidably received in the T-shaped trench (42) and an engaging block (443) embedded in or separated from the engaging trench (43).Type: GrantFiled: May 26, 2022Date of Patent: April 1, 2025Assignee: GALEMED CORPORATIONInventors: Po-Chang Chen, Hsin-Chen Wang, Chia-Chin Yang, Hao-Hsiang Chen, Chun-Wei Hsu
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Patent number: 12263410Abstract: In non-limiting examples of the present disclosure, systems, methods, and devices for matching device configurations to games are presented. A set of device configuration tiers may be generated from gameplay telemetry data generated by a plurality of client devices executing a plurality of games. A device configuration for a specific client device may be determined based at least on the specific client device's GUI type. When the specific client device accesses a software game library a determination may be made based on a performance tier corresponding to the device configuration for the specific client device as to whether the specific client device can adequately execute each game. One or more recommendations may be rendered and displayed in the game library based on the determination of whether the specific client device can adequately execute each game.Type: GrantFiled: October 19, 2023Date of Patent: April 1, 2025Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Arunabh Verma, Rajneil Singh Rana, Seyed Ali Hosseini Khayat, Matthew Carl Dubois, Daniel Aaron Dobyns, Sebastian Carl Merry, Griffin Solimini, Shu-Wei Hsu, William Jarrad Bailey, Timothy John Kiesow, Eric Hamilton, Kripal Kavi
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Patent number: 12265412Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.Type: GrantFiled: April 11, 2024Date of Patent: April 1, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
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Publication number: 20250103914Abstract: In some aspects, the techniques described herein relate to a method including: determining a first cross-entropy loss, wherein the first cross-entropy loss is determined based on a set of predictions, and wherein the set of predictions are based on a classifier head of a machine learning model generating the set of predictions based on a set of feature vectors; updating the classifier head and a prompt of the machine learning model with the first cross-entropy loss; generating outlier samples based on the set of feature vectors; providing, as input to the classifier head, the set of feature vectors and the outlier samples, wherein a second cross-entropy loss and an outlier regularization loss are computed by the classifier head based on the set of feature vectors and the outlier samples; and updating the classifier head with the second cross-entropy loss and the outlier regularization loss.Type: ApplicationFiled: September 27, 2023Publication date: March 27, 2025Inventors: Wei-Cheng HUANG, Richard CHEN, Hsiang HSU
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Publication number: 20250107117Abstract: A Schottky diode includes a substrate with an epitaxy layer on which a cathode region and an anode region are defined. A cathode structure and an anode structure are formed in the cathode region and the anode region respectively and horizontally separated by a distance. The anode structure includes a plurality of p-type doped regions diffused from the epitaxy layer toward the substrate, with an interval is formed between adjacent two p-type doped regions. A backside metal film and a backside protection layer are sequentially formed on a back surface of the substrate. Since the manufacturing of the Schottky diode does not involve wire bonding and molding processes, the overall thickness of the Schottky diode is reduced and heat dissipation is improved. With the backside metal film on the back side of the substrate, an equivalent resistance and a forward voltage of the Schottky diode can be reduced.Type: ApplicationFiled: November 15, 2023Publication date: March 27, 2025Inventors: CHUNG-HSIUNG HO, CHI-HSUEH LI, CHIA-WEI CHEN, YU-MING HSU, WEN-LIANG HUANG, MING-KUN HSIN, SHIH-MING CHEN