Abstract: In an integrated circuit (IC) fabrication process, devices or sub-circuits are fabricated in respective first and second electrical isolation regions. A back-to-back (B2B) diodes sub-circuit is fabricated in a third electrical isolation region, which includes a first diode whose cathode is connected with a first terminal and whose anode is connected with a second terminal, and a second diode whose anode is connected with the first terminal and whose cathode is connected with the second terminal. Electrostatic discharge protection is provided to the first and second electrical isolation regions by electrically connecting the first terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the first device or sub-circuit and the second terminal of the B2B diodes sub-circuit with a VSS power supply terminal of the second device or sub-circuit. Thereafter, the first device or sub-circuit and the second device or sub-circuit are electrically connected.

Abstract: A Class-D audio amplifier includes a triangular wave generator, a wave reshaping device and a pulse-width modulator. The triangular wave generator generates a first triangular wave. The wave reshaping device generates a second triangular wave by reshaping the first triangular wave. The pulse-width modulator modulates a pair of differential audio input waves with the second triangular wave instead of the first triangular wave to reduce a switching loss of the Class-D audio amplifier.

Abstract: Partial barrier-free vias and methods for forming such are disclosed herein. An exemplary interconnect structure of a multilayer interconnect feature includes a dielectric layer. A cobalt-comprising interconnect feature and a partial barrier-free via are disposed in the dielectric layer. The partial barrier-free via includes a first via plug portion disposed on and physically contacting the cobalt-comprising interconnect feature and the dielectric layer, a second via plug portion disposed over the first via plug portion, and a via barrier layer disposed between the second via plug portion and the first via plug portion. The via barrier layer is further disposed between the second via plug portion and the dielectric layer. The cobalt-comprising interconnect feature can be a device-level contact or a conductive line of the multilayer interconnect feature. The first via plug portion and the second via plug portion can include tungsten, cobalt, and/or ruthenium.

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.

Abstract: A semiconductor device package includes a supporting element, a transparent plate disposed on the supporting element, a semiconductor device disposed under the transparent plate, and a lid surrounding the transparent plate. The supporting element and the transparent plate define a channel.

Abstract: The invention discloses a semiconductor package antenna structure and its manufacturing method, wherein the semiconductor package antenna structure includes a first substrate, a semiconductor chip, and a second substrate. The first substrate has at least two stacked first redistribution layers, and each of the first redistribution layers has a first dielectric layer, a first patterned metal layer, and/or a first conductive pillar layer. The semiconductor chip is embedded in the first substrate and coupled to the first redistribution layers. The second substrate has a second redistribution layer, a second conductive pillar layer, and an air dielectric layer, wherein the second conductive pillar layer is protruded from the second redistribution layer. The second substrate is connected to the first substrate by a second conductive pillar layer, and the air dielectric layer is located between the second redistribution layer, the second conductive pillar layer, and the first substrate.

Abstract: An electronic component inspection device and an electronic component inspection method are provided. The electronic component inspection device includes a carrier, a heating module, and an inspection module. The carrier carries the electronic component. The heating module includes a first heating source and a second heating source. The first heating source is placed on one side of the carrier and irradiates one surface of the electronic component. The second heating source is placed on the other side of the carrier and irradiates the other surface of the electronic component. The inspection module includes a moving mechanism and an inspection probe mounted on the moving mechanism. The moving mechanism is arranged corresponding to the carrier and drives the inspection probe to test the electronic component.

Abstract: A circuit includes an operational amplifier configured to output a driving signal according to a feedback voltage associated with an output voltage and a reference voltage, a pass gate circuit comprising switches in current paths, and hysteresis comparators connected to the operational amplifier and configured to generate control signals to separately turn on or off the switches in the current paths in response to the driving signal.

Abstract: A device includes a first 2D semiconductor layer over a substrate, a first source/drain contact interfacing a first region of the first 2D semiconductor layer, and a second source/drain contact interfacing a second region of the first 2D semiconductor layer spaced apart from the first region of the first 2D semiconductor layer. The first source/drain contact includes an antimony layer interfacing the first region of the first 2D semiconductor layer, and a platinum layer over the antimony layer.

Abstract: An integrated fan-out (InFO) package includes a die, an encapsulant, and a horn antenna. The die has an active surface and a rear surface opposite to the active surface. The encapsulant laterally encapsulates the die. The horn antenna is electrically connected to the die. The horn antenna includes a top wall and a bottom wall respectively located on two opposite sides of the die and the encapsulant. A portion of the top wall is located within a span of the active surface of the die. A portion of the bottom wall is located within a span of the rear surface of the die.

Abstract: A method for forming a semiconductor structure is provided. The method includes forming a first fin structure over a first region of a substrate and forming a second fin structure over a second region of a substrate, forming a first gate dielectric layer around the first fin structure and forming a second gate dielectric layer around the second fin structure, forming a barrier layer over the first gate dielectric layer, treating the substrate with a first fluorine-containing gas, forming a work function layer over the second gate dielectric layer after treating the substrate with the first fluorine-containing gas, and treating the substrate with a second fluorine-containing gas after forming the work function layer over the second gate dielectric layer.

Abstract: A video coder receives data for a block of pixels to be encoded or decoded as a current block of a current picture of a video. The video coder receives a set of transform coefficients of the current block. The video coder identifies multiple transform hypotheses. Each hypothesis includes two or more predicted transform parameters. The video coder computes a cost for each hypothesis by performing inverse transform on the transform coefficients of the current block according to the predicted transform parameters of the hypothesis. The video coder signals or receives a codeword that identifies a first transform mode of a first transform parameter. The codeword is assigned to the first transform mode based on the calculated costs of the multiple transform hypotheses. The video coder encodes or decodes the current block by reconstructing the current block according to the identified first transform mode.

Abstract: A method for signaling arbitrary partition boundaries is provided. A video coder derives a partitioning structure for splitting the current block by identifying a partitioning position having a lowest cost. The video coder splits the current block into first and second partitions according to the identified partitioning position. The video coder encodes or decodes the first and second partitions of the current block. The first and second partitions may be associated with first and second templates that are constructed based on reconstructed pixels neighboring the current block. The video coder may identify the partitioning position by computing a first cost based on the first template and a second cost based on the second template and optimizing the partitioning position to minimize a sum of the first and second costs.

Abstract: An integrated circuit includes a photodetector. The photodetector includes one or more dielectric structures positioned in a trench in a semiconductor substrate. The photodetector includes a photosensitive material positioned in the trench and covering the one or more dielectric structures. A dielectric layer covers the photosensitive material. The photosensitive material has an index of refraction that is greater than the indices of refraction of the dielectric structures and the dielectric layer.

Abstract: An integrated circuit includes a first active region, a first contact, a first and second conductor and a first and second via. The first active region extends in a first direction, and is on a first level of a substrate. The first contact extends in a second direction, is on a second level, and overlaps the first active region. The first conductor extends in the first direction, overlaps the first contact, and is on a third level. The second conductor extends in the first direction, is on the third level, overlaps the first contact, and is separated from the first conductor in the second direction. The first via is between the first contact and first conductor, and electrically couples the first contact and the first conductor together. The second via is between the first contact and the second conductor, and electrically couples the first contact and the second conductor together.

Abstract: A method for predicting collision detection of moving path of machine tool includes the following steps. Firstly, the motion information of a processing unit is acquired through the data acquisition unit. Then, based on the motion information, the arithmetic unit calculates the stop position of the processing unit after deceleration; and, further based on the stop position of the processing unit, the collision detection unit performs anti-collision detection to compare the stop position of the processing unit and the workpiece position of the workpiece. In additional, a system for predicting collision detection of moving path of machine tool is also provided.

Abstract: A rotor is a rotor rotatable about a central axis, and includes a rotor core and a plurality of flux barrier groups provided in the rotor core and arranged at intervals in a circumferential direction. Each of a plurality of the flux barrier groups includes a plurality of flux barriers arranged side by side at intervals in a radial direction, the rotor core has a projecting portion projecting from an edge portion of the flux barrier toward the inside of the flux barrier, and in each of a plurality of the flux barrier groups, an edge portion of at least one of the flux barriers is provided with two or more of the projecting portions.

Abstract: A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a first metal gate layer for the P-type transistors and a second metal gate layer for the N-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistors.

Abstract: A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. A suction system removes pad conditioner debris and the slurry from the pad.

Abstract: An antenna includes a grounding plate; a first electric dipole; a first feeding unit, where the first feeding unit includes a first coupling structure coupled to the first electric dipole, and the first feeding unit performs coupled feeding on the first electric dipole through the first coupling structure; a second electric dipole, where the second electric dipole is disposed between the first electric dipole and the grounding plate; a second feeding unit, where the second feeding unit includes a second coupling structure coupled to the second electric dipole, and the second feeding unit performs coupled feeding on the second electric dipole through the second coupling structure; and a magnetic dipole, where the magnetic dipole is electrically connected to the grounding plate, the first electric dipole, and the second electric dipole.