Abstract: Video processing methods and apparatuses in a video encoding or decoding system for processing a video picture partitioned into blocks with one or more partition constraints. The video encoding or decoding system receives input data of a current block and checks whether a predefined splitting type is allowed to partition the current block according to first and second constraints. The first constraint restricts each sub-block partitioned from the current block to be completely contained in one pipeline unit, and the second constraint restricts each sub-block partitioned from the current block to contain one or more complete pipeline units. The pipeline units are non-overlapping units in the video picture designed for pipeline processing. The current block is not partitioned by the predefined splitting type if any sub-block partitioned by the predefined splitting type violates both the first and second constraints. The system encodes or decodes the current block.

Abstract: A method for specifying layout of subpictures in video pictures is provided. A video decoder receives data from a bitstream to be decoded as a current picture of a video. For a current subpicture of a set of subpictures of the current picture, the video decoder determines a position of the current subpicture based on a width and a height of the current picture and a previously determined width and height of a particular subpicture in the set of subpictures. The video decoder reconstructs the current picture and the current subpicture based on the determined position.

Abstract: A method includes steps of: storing an entry of sensing data in a storage area of a storage module of a board management controller as sensor data; assigning a buffer area of the storage module with a locked state; copying the sensor data from the storage area to the buffer area; and assigning the buffer area with an unlocked state. A processing module of the board management controller does not respond to a request to access the sensor data when the buffer area is assigned with the locked state, and responds to the request to access the sensor data when the buffer area is assigned with the unlocked state.

Abstract: A semiconductor structure includes a substrate, a fin-shaped structure protruding from the substrate and orienting lengthwise along a first direction, an isolation feature disposed over the substrate and along a sidewall of a bottom portion of the fin-shaped structure, and a metal gate structure disposed over the fin-shaped structure and the isolation feature and orienting lengthwise along a second direction perpendicular to the first direction. The metal gate structure includes a bottom portion sandwiched between the isolation feature and the bottom portion of the fin-shaped structure along the second direction.

Abstract: A process tool including a polishing pad on a top surface of a wafer platen. A wafer carrier is configured to hold a wafer over the polishing pad. A slurry dispenser is configured to dispense an abrasive slurry including a plurality of charged abrasive particles having a first polarity onto the polishing pad. A first conductive rod is within the wafer platen and coupled to a first voltage supply. A wafer roller is configured to support the wafer. A first wafer brush is arranged beside the wafer roller. A second conductive rod is within the first wafer brush and coupled to a second voltage supply. The first voltage supply is configured to apply a first charge having a second polarity, opposite the first polarity, to the first conductive rod. The second voltage supply is configured to apply a second charge having the second polarity to the second conductive rod.

Abstract: An EUV radiation source apparatus includes an EUV source vessel including a chamber; a crucible disposed in the chamber; a tin layer disposed on the crucible; a catcher disposed in the chamber and configured to collect fuel debris generated from a collision of the tin layer and a laser beam; a heat dissipation structure disposed over the catcher; and a venting system coupled to the EUV source vessel and communicable with the chamber. A method for generating EUV radiation includes: collecting fuel debris on a catcher disposed in a chamber of an EUV source vessel; dissipating heat from the catcher to the chamber; and venting a gas out of the EUV source vessel to cool the chamber to a decreased temperature through an opening disposed on the EUV source vessel.

Abstract: A semiconductor device includes a semiconductor substrate having a first protected circuit; a first guard ring; and a second guard ring adjacent to the first guard ring and around the first protected circuit. The second guard ring includes a first via tower configured to provide a first reference voltage; a second via tower configured to provide a second reference voltage different than the first reference voltage; and at least a third via tower configured to provide the first reference voltage.

Abstract: An EUV radiation source apparatus includes an EUV source vessel; a tin layer disposed in the EUV source vessel; a chamber disposed adjacent to the EUV source vessel; and a first filter disposed in the chamber, wherein the first filter includes a membrane and a mesh disposed on the membrane, and the membrane and the mesh are integrally formed. A method for generating EUV radiation includes: forming a first filter including a membrane and a mesh integrally formed with the membrane; disposing the first filter in a chamber adjacent to an EUV source vessel; and collecting fuel debris on the first filter in the chamber.

Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Abstract: A static random access memory (SRAM) cell includes a write port including a first inverter including a first pull-up transistor and a first pull-down transistor, and a second inverter including a second pull-up transistor and a second pull-down transistor and cross-coupled with the first inverter; and a read port including a read pass-gate transistor and a read pull-down transistor serially connected to each. A first doped concentration of impurities doped in channel regions of the second pull-down transistor and the read pull-down transistor is greater than a second doped concentration of the impurities doped in a channel region of the first pull-down transistor, or the impurities are doped in the channel regions of the second pull-down transistor and the read pull-down transistor and are not doped in the channel region of the first pull-down transistor.

Abstract: An electronic apparatus is provided. The electronic apparatus includes an integrated fan-out package, a dielectric housing, and a plurality of conductive patterns. The dielectric housing is covering the integrated fan-out package, wherein a gap or a first dielectric layer is in between the dielectric housing and the integrated fan-out package. The plurality of conductive patterns is located on a surface of the dielectric housing, wherein the plurality of conductive patterns is located in between the dielectric housing and the integrated fan-out package.

Abstract: A semiconductor package includes a first die structure, a first redistribution structure that is disposed on the first die structure, a second die structure that is disposed on the first redistribution structure, and a second redistribution structure that is disposed on the second die structure. The first die structure includes an interposer, and the interposer includes a semiconductor substrate and through-vias that penetrate through the semiconductor substrate. A first integrated circuit die is disposed in the semiconductor substrate of the interposer. The second die structure includes a second integrated circuit die that is encapsulated in an encapsulant and several conductive pillars that penetrate through the encapsulant. The first integrated circuit die is electrically connected to the second integrated circuit die through the first redistribution structure, the conductive pillars, and the second redistribution structure.

Abstract: The present disclosure relates to a system, a method and a computer-readable medium for quality prediction. The method includes obtaining values of a parameter of a first endpoint, obtaining values of a parameter of a second endpoint, and generating a prediction of the parameter of the first endpoint according to the values of the parameter of the first endpoint and the values of the parameter of the second endpoint. The prediction includes probability distribution information of the parameter of the first endpoint at a timing in the future. The present disclosure can result in a more precise quality prediction.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate; forming a first gate mask over the fin, the first gate mask having a first width; forming a second gate mask over the fin, the second gate mask having a second width, the second width being greater than the first width; depositing a first filling layer over the first gate mask and the second gate mask; depositing a second filling layer over the first filling layer; planarizing the second filling layer with a chemical mechanical polish (CMP) process, the CMP process being performed until the first filling layer is exposed; and planarizing the first filling layer and remaining portions of the second filling layer with an etch-back process, the etch-back process etching materials of the first filling layer, the second filling layer, the first gate mask, and the second gate mask at the same rate.

Abstract: A switched capacitor voltage converter circuit for converting a first voltage to a second voltage, includes: a switched capacitor converter and a control circuit. The switched capacitor converter includes at least two capacitors, plural switches and at least one inductor. In a mode switching period wherein the switched capacitor converter switches from a present conversion mode to a next conversion mode, at least two forward switches of the plural switches operate in a unidirectional conduction mode. Each of the forward switches provides a current channel that unidirectionally flows toward the second voltage in the unidirectional conduction mode. The switched capacitor voltage converter circuit is also operable to convert the second voltage to the first voltage.

Abstract: A light-emitting device is provided. The light-emitting device includes a circuit substrate, an array substrate, a plurality of light-emitting units and a driver. The circuit substrate has a top surface. A top circuit is disposed on the top surface. The array substrate is disposed on the top surface of the circuit substrate and electrically connected to the top circuit. The light-emitting units are disposed on the array substrate. The light-emitting device further includes an electrical connection structure, a plurality of light extraction layers, a protective layer, a plurality of test pads, and a light absorption layer. The plurality of test pads are disposed on the array substrate, and the light absorption layer covers at least one of the test pads.

Abstract: A semiconductor device includes a substrate, a fin structure protruding from the substrate, a gate insulating layer covering a channel region formed of the fin structure, a gate electrode layer covering the gate insulating layer, and isolation layers disposed on opposite sides of the fin structure. The fin structure includes a bottom portion, a neck portion, and a top portion sequentially disposed on the substrate. A width of the neck portion is less than a width of the bottom portion and a width of a portion of the top portion.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a gate structure formed over nanostructures. The gate structure includes a gate dielectric layer, and a fill layer over the gate dielectric layer. The semiconductor device structure includes a protection layer formed over the fill layer, and a gate spacer layer formed adjacent to the gate structure. The semiconductor device structure includes an insulating layer formed over the protection layer, and the insulating layer is in direct contact with the gate spacer layer.

Abstract: One aspect of a rotor of the present disclosure is a rotor that includes a rotor core extending along the axial direction and a plurality of auxiliary magnets disposed in the rotor core. The rotor core includes a slit group including a plurality of first slits aligned in a radial direction, and a second slit disposed radially inside the slit group when viewed from the axial direction. The first slit extends along the circumferential direction in a shape protruding radially inward when viewed from the axial direction. The second slit includes a magnet housing portion extending along the radial direction, and a pair of outer flux barrier portions. The auxiliary magnet is disposed in the magnet housing portion with the circumferential direction as the magnetization direction.