Abstract: A semiconductor device includes a substrate, an outer detection wire and an inner detection wire. The substrate has a periphery lateral surface. The outer detection wire is disposed on the substrate and adjacent to the periphery lateral surface. The inner detection wire is disposed on the substrate, adjacent to the periphery lateral surface, and isolated from the outer detection wire. The outer detection wire is closer to the periphery lateral surface than the inner detection wire.

Abstract: A vehicle device includes a heat sink, a retaining wall, at least one electronic component, a fan and an upper cover. The heat sink has a drainage portion and an electronic component accommodating portion, in which the drainage portion has a fan accommodating portion. The retaining wall isolates the drainage portion and the electronic component accommodating portion. The at least one electronic component is disposed over the electronic component accommodating portion. The fan is disposed over the fan accommodating portion. The upper cover covers the heat sink, the retaining wall, the at least one electronic component and the fan, and has through holes and at least one first drain outlet, in which the through holes are aligned with the drainage portion, and the at least one first drain outlet is adjacent to an edge portion of the drainage portion and away from the fan.

Abstract: A de-flicker system includes a compensation gain estimation circuit and a flicker removal circuit. The compensation gain estimation circuit receives a plurality of flicker-dependent frames with sliding bandings, and estimates a compensation gain for each of the plurality of flicker-dependent frames according to the flicker-dependent frames. The flicker removal circuit applies flicker compensation to each of the flicker-dependent frames according to the compensation gain.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a drain contact on opposing sides of the epitaxial layer of the source contact, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, and wherein the breakdown voltage enhancement and leakage prevention structure comprises a reduced surface field (RESURF) structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a body region and a plurality of gates formed in the epitaxial layer, an interlayer dielectric layer over the epitaxial layer, a gate-source electrostatic discharge (ESD) diode in the interlayer dielectric layer, a source contact connected to the source and a first terminal of the gate-source ESD diode structure, a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, a drain contact on opposing sides of the epitaxial layer of the source contact, a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: A method includes growing an epitaxial layer over a substrate, forming a plurality of gates in the epitaxial layer, forming a breakdown voltage enhancement and leakage prevention structure in the epitaxial layer, comprising a reduced surface field (RESURF) structure, forming a source in the epitaxial layer and a gate-source Electrostatic Discharge (ESD) diode structure over the epitaxial layer, forming a source contact connected to the source and a first terminal of the gate-source ESD diode structure, forming a gate contact connected to the plurality of gates and a second terminal of the gate-source ESD diode structure, and forming a drain contact on the opposing side of the epitaxial layer from the source contact.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure, wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: An apparatus includes a drain and a source on opposing sides of an epitaxial layer, a plurality of gates formed in the epitaxial layer, a source contact connected to the source, a gate contact connected to the plurality of gates, a gate-source electrostatic discharge (ESD) diode connected between the gate contact and the source contact, and a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure.

Abstract: A preparation method of a monometallic or bimetallic nanoparticle-supported catalyst is disclosed. The synthesis of metal nanoparticles with different shapes, sizes, and atomic structures is affected by nucleation and growth rates. By changing a ratio of strong and weak reducing agents, a suitable double reducing agent is provided for metal nanoparticles with different reduction potentials, where the strong reducing agent is used for rapid nucleation and the weak reducing agent is used for the growth of metal nanoparticles. Accordingly, modulation and control of the nucleation and growth rates can be realized during the synthesis of nanoparticles. In addition, through multiple actions of a combination of reducing agents with different reduction intensities, monometallic/bimetallic nanoparticles of different sizes, shapes, and atomic structures are controllably prepared, which are then supported with a carrier to obtain the monometallic or bimetallic nanoparticle-supported catalyst.

Abstract: Generally this disclosure describes a video communication system that replaces actual live images of the participating users with animated avatars. A method may include selecting an avatar; initiating communication; detecting a user input; identifying the user input; identifying an animation command based on the user input; generating avatar parameters; and transmitting at least one of the animation command and the avatar parameters.

Abstract: An image registration method is read by a processing device to perform: obtaining a first medical image and a second medical image generated by different imaging devices, with the first medical image including soft and hard tissue image; segmenting the first medical image and the second medical image to obtain a first hard tissue image and a second hard tissue image, respectively; aligning a coordinate axis of the first hard tissue image and a coordinate axis of the second hard tissue image, and obtaining a registration field indicating a corresponding relationship between the first hard tissue image and the second hard tissue image; obtaining a scale ratio between the first hard tissue image and the second hard tissue image according to the registration field; and generating a target soft and hard tissue image according to the scale ratio, the soft and hard tissue image and the second hard tissue image.

Abstract: A semiconductor device includes a first semiconductor component, a second semiconductor component, and a damage detection structure. The first semiconductor component includes a first edge region. The second semiconductor component is stacked below the first semiconductor component and includes a second edge region. The damage detection structure includes a plurality of first conductive paths and a plurality of second conductive paths. The first conductive paths are disposed in the first edge region. The second conductive paths are disposed in the second edge region and are electrically coupled to the first conductive paths.

Abstract: In a computer network, communication connections may be established between client devices and network devices. An algorithm may be generated and used as a method to identify and resolve issues with Uplink communications between client devices and network devices. When an issue with an Uplink communication is identified, a total number of issues with the communication may be determined. Determining that the total number of issues with a communication is greater than a threshold, the client device associated with the communication may be deauthenticated from the respective network device. After a client device is deauthenticated from a network device, the total number of deauthentications may be determined with the network device. Determining the total number of deauthentications with a network device is greater than a threshold, the radio of the network device may be disabled to deauthenticate all connected client devices. Solutions may be implemented according to the issues identified.

Abstract: A die includes a plurality of pillar bumps configured to electrically connect the die to a substrate. The plurality of pillar bumps includes at least one first pillar bump having a first total pillar bump height. The at least one first pillar bump includes a first pillar having a first pillar height and a first solder cap having a first solder cap height. The plurality of pillar bumps includes at least one second pillar bump having a second pillar height substantially equal to the first total pillar bump height. The at least one second pillar bump includes a second pillar having a second pillar height and a second solder cap having a second solder cap height. The second pillar height is greater than the first pillar height, and the second solder cap height is less than the first solder cap height.

Abstract: Disclosed are a bulk acoustic wave resonator and a fabrication method for the bulk acoustic wave resonator. The fabrication method includes: preparing a cavity with a top opening on a first silicon wafer; preparing an insulating layer on an upper surface of a second silicon wafer, and preparing a resonant piezoelectric stack on an upper surface of the insulating layer; preparing a first silicon dioxide layer on an upper surface of the resonant piezoelectric stack; bonding a surface where the top opening of the cavity is located with an upper surface of the first silicon dioxide layer; and preparing a lead out pad of the first electrode and the second electrode.

Abstract: The present disclosure provides a semiconductor package including a first integrated circuit die having a first on-die test ring thereon; a second integrated circuit die having a second on-die test ring thereon; and a system test ring constructed by connecting the first on-die test ring and the second on-die test ring. The system test ring allows for detection of damage to the individual integrated circuit die assembled in one package on a system level.

Abstract: A semiconductor die includes a substrate comprising an integrated circuit region thereon, a front end of line (FEOL) portion disposed on a front side of the substrate, a back end of line (BEOL) portion disposed on the FEOL portion, a power delivery network (PDN) portion disposed on a back side of the substrate, and a plurality of through substrate vias penetrating through the substrate and disposed along a perimeter of the integrated circuit region. The BEOL portion includes a first discontinuous ring disposed along the perimeter of the integrated circuit region. The PDN portion includes a second discontinuous ring disposed along the perimeter of the integrated circuit region. The first discontinuous ring is interlaced with the second discontinuous ring through the plurality of through substrate vias, thereby constituting a die damage ring.

Abstract: A vehicle bracket includes a base, a connecting piece and a fixing piece. A first surface of the base is configured to face a mounting surface. The base has a set of pivoting portions and a set of abutting portions on a second surface thereof. The set of abutting portions is configured to abut against a portion of a vehicle device. A first end of the connecting piece is rotationally and pivotally connected to the set of pivoting portions, and a second end thereof has a rod portion protruding laterally from the connecting piece. The rod portion is configured to be inserted into a guide groove of the vehicle device, so that the rod portion is limited to slide in the guide groove. The fixing piece is configured to fix the set of abutting portions and the portion of the vehicle device to each other.