Abstract: A new method of forming selective salicide is described, whereby low resistance salicide is formed on exposed MOSFET CMOS, narrow polysilicon gates and lightly doped source/drains (LLD) without affecting device electrical performance. This invention describes a selective salicide process forming titanium salicide on exposed MOSFET CMOS devices using ion implantation for effective ion mixing between a two-step titanium deposition process. First, a thin layer of titanium is deposited on exposed polysilicon gate and exposed lightly doped source/drain (LLD) regions. Second, a low energy ion implantation of Si+ is performed with peak dose targeted to be just below the Ti/Si interface. Third, an initial rapid thermal anneal (RTA) is performed followed by a selective etch to remove unwanted, excess titanium. The final step is another rapid thermal anneal (RTA) to fully convert the silicide from C49 crystal structure to the preferred C54 structure, for low resistivity.

Abstract: A method of forming aluminum guard structures in copper interconnect structures, used to protect the copper interconnect structures from a laser write procedure, performed to an adjacent copper fuse element, has been developed. The method features forming guard structure openings in an upper level of the copper interconnect structures, in a region adjacent to a copper fuse element. Deposition and patterning of an aluminum layer result in the formation of aluminum guard structures, located in the guard structure openings. The aluminum guard structures protect the copper interconnect structures from the oxidizing and corrosive effects of oxygen, fluorine and water ions, which are generated during a laser write procedure, performed to the adjacent copper fuse element.

Abstract: A sheet feeding apparatus to be used in an automatic sheet feeder having a motor rotatable in a first direction and a second direction is disclosed.

Abstract: A method for creating a self-aligned channel implant with elevated source/drain areas. Forming a thin dielectric layer on top of a silicon substrate, a thick layer of oxide is deposited over this dielectric. An opening is exposed and etched through the layer of oxide, through the dielectric and into the underlying silicon substrate creating a shallow trench in the substrate. By performing the channel implant LDD implant, pocket implant, forming the gate spacers and electrode, removing the thick layer of oxide and forming the S/D regions a gate electrode has been created with elevated S/D regions. By forming the gate spacers, performing channel implant, forming the gate electrode, removing the thick layer of oxide and performing S/D implant a gate electrode has been created with elevated S/D regions and disposable spacers.

Abstract: The present invention discloses a framework system for testing server with mixed workloads and a test method thereof, comprising workload case configure utility interface which includes function that let the framework invoke the third party's workload configure utilities to define workload cases for various test purpose; and workload interface which includes function of workload setup, control and monitor. The advantage of the invention is that the third party can flexibly adds his workloads into the framework system via a workload case configure utility interface and a workload interface.

Abstract: A process for forming a dual damascene opening, in a composite insulator layer, comprised of an overlying, wide diameter opening, used to accommodate a metal interconnect structure, and comprised of an underlying, narrow diameter opening, used to accommodate a metal via structure, has been developed. The process features the use of conventional photolithographic and anisotropic dry etching procedures, used to create an initial dual damascene opening, in the composite insulator layer. The subsequent formation of insulator spacers, on the vertical sides of the initial dual damascene opening, however, results in a final dual damascene opening, featuring a diameter smaller than the diameter displayed with the initial dual damascene opening.

Abstract: A method for forming both n and p wells in a semiconductor substrate using a single photolithography masking step, a non-conformal oxide layer and a chemical-mechanical polish step. A screen oxide layer is formed on a semiconductor substrate. A barrier layer is formed on the screen oxide layer. The barrier layer is patterned to form a first opening in the barrier layer over regions of the substrate where first wells will be formed. We implant impurities of a first conductivity type into the substrate to form first wells. In a key step, a non-conformal oxide layer is formed over the first well regions and the barrier layer. It is critical that the non-conformal oxide layer formed using a HDPCVD process. The non-conformal oxide layer is chemical-mechanical polished stopping at the barrier layer. The barrier layer is removed using a selective etch, to form second openings in the remaining non-conformal oxide layer over areas where second well will be formed in the substrate.

Abstract: A method of forming a FET with an having a self-aligned pocket implant, comprising the following steps. A substrate is formed having a substrate dielectric layer thereon and a first oxide layer over the substrate dielectric layer. The first oxide layer having an upper surface. A trench is formed through the oxide layer, the substrate dielectric layer, and partially through the substrate. The trench having a bottom and side walls. A second oxide layer is formed along the bottom and said side walls of said trench within the substrate. A dopant is selectively ion implanted into the substrate is achieved to form lightly doped layers adjacent the side walls of the trench within the substrate. A self-aligned channel implant and a pocket implant are ion implanted at predetermined respective depths in the substrate below the trench bottom is achieved. Side-wall spacers on the side walls of the trench are then formed with the side-wall spacers each having a top surface below the upper surface of the first oxide layer.

Abstract: A new method for forming polysilicon lines using a SiON anti-reflective coating during photolithography wherein a thin oxide protection layer is formed over the polysilicon sidewalls and active area surfaces after etching to prevent damage caused by removal of the SiON in the fabrication of integrated circuits is achieved. A gate oxide layer is provided on the surface of a silicon substrate. A polysilicon layer is deposited overlying the gate oxide layer. A SiON anti-reflective coating layer is deposited overlying the polysilicon layer. A photoresist mask is formed over the SiON anti-reflective coating layer. The SiON anti-reflective coating layer, polysilicon layer, and gate oxide layer are etched away where they are not covered by the photoresist mask to form polysilicon lines. The polysilicon lines and the silicon substrate are oxidized to form a protective oxide layer on the sidewalls of the polysilicon lines and on the surface of the silicon substrate.

Abstract: A survival hood including a hood for the head and neck, which has an inside pocket with at least one upward open space, and a gas generator put in the pocket inside the hood to release oxygen through a chemical reaction for breathing when it is bent inwards to break an inside chemical solution container.