Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contact formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.

Abstract: Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (MTJ) structures are provided. An exemplary method for fabricating an integrated circuit includes forming an MTJ structure including a top electrode layer. The MTJ structure has a first sidewall and a second sidewall separated from the first sidewall by a first width. The method includes forming a conductive etch stop on the top electrode layer. The conductive etch stop has a second width greater than the first width. The method also includes depositing dielectric material over the conductive etch stop and the MTJ structure. The method further includes etching the dielectric material to form a trench exposing the conductive etch stop. Also, the method includes forming a conductive via in the trench over and in electrical communication with the conductive etch stop.

Abstract: A method for forming a stacking structure, including forming a ruthenium oxide layer over a substrate; forming a praseodymium oxide layer over the ruthenium oxide layer; and forming a titanium oxide layer over the praseodymium oxide layer; wherein the titanium oxide layer has a rutile phase with the existence of the praseodymium oxide layer underneath. The oxide layers are deposited by a plurality of atomic layer deposition cycles using ruthenium precursor, praseodymium precursor, titanium precursor, and ozone.

Abstract: A method for forming a stacking structure, including forming a ruthenium oxide layer over a substrate; forming a praseodymium oxide layer over the ruthenium oxide layer; and forming a titanium oxide layer over the praseodymium oxide layer; wherein the titanium oxide layer has a rutile phase with the existence of the praseodymium oxide layer underneath. The oxide layers are deposited by a plurality of atomic layer deposition cycles using ruthenium precursor, praseodymium precursor, titanium precursor, and ozone.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.

Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Abstract: A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.

Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate.