Patents by Inventor Wei-Hui Hsu

Wei-Hui Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100200903
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Application
    Filed: April 26, 2010
    Publication date: August 12, 2010
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Patent number: 7754614
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: July 13, 2010
    Assignee: Nanya Technologies Corporation
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Patent number: 7696108
    Abstract: A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.
    Type: Grant
    Filed: December 9, 2007
    Date of Patent: April 13, 2010
    Assignee: Nanya Technology Corporation
    Inventors: Wen-Chieh Wang, Jin-Tau Huang, Wei-Hui Hsu, Tse-Yao Huang
  • Publication number: 20090061612
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Application
    Filed: January 17, 2008
    Publication date: March 5, 2009
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Publication number: 20090023300
    Abstract: A method of forming a shadow layer on a wafer bevel region is provided. First, a substrate having the wafer bevel region and a central region is provided. Thereafter, an upper insulator and a lower insulator are provided. The upper insulator is disposed on an upper surface of the substrate and at least covers the central region. The lower insulator is disposed on a lower surface of the substrate and at least covers the central region. A shadow layer is then formed on the upper surface which is not covered by the upper insulator and on the lower surface which is not covered by the lower insulator. Next, the upper insulator and the lower insulator are removed.
    Type: Application
    Filed: December 9, 2007
    Publication date: January 22, 2009
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Wen-Chieh Wang, Jin-Tau Huang, Wei-Hui Hsu, Tse-Yao Huang
  • Publication number: 20090017604
    Abstract: A method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device comprises providing a substrate. Under an atmosphere containing a fluoride nitride compound, a plasma treatment process is performed to simultaneously fluorinate and nitrify a surface of the substrate. Thereafter, a dielectric layer is formed on the substrate.
    Type: Application
    Filed: November 1, 2007
    Publication date: January 15, 2009
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Mao-Ying WANG, Jer-Chyi WANG, Wei-Hui HSU, Liang-Pin CHOU, Kuo-Hui SU, Chang-Rong WU, Chao-Sung LAI