Patents by Inventor Wei-Hui Hsu

Wei-Hui Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10768673
    Abstract: A hinge structure including a first screw rod, a sliding rod, and a second screw rod is provided. The first screw rod comprises a threaded shaft. The sliding rod is sleeved on the threaded shaft. The second screw rod is sleeved on the sliding rod. The threaded shaft has a first helical slot. The sliding rod has a first guiding portion and a second guiding portion, and the first guiding portion is coupled to the first helical slot. The second screw rod has a second helical slot, and the second guiding portion is coupled to the second helical slot.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: September 8, 2020
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Chih Hsu, Ya-Hui Tseng, Chang-Kai Liu, Ming-Shun Lu, Wen-Jie Hsiao
  • Publication number: 20200272327
    Abstract: A computer system including an electronic device and an input device is disclosed. The electronic device includes a touch display area and a control unit. The input device includes a plurality of positioning structures and a grounding piece. The positioning structures are electrically connected to the grounding piece. When the input device is disposed on the touch display area of the electronic device, the control unit detects positions of the positioning structures on the touch display area, calculates a coverage area covered by the input device on the touch display area according to the positions, and determines a range of a display area of the touch display area according to the coverage area.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 27, 2020
    Inventors: Ching-Fu HSU, Wei-Ting WONG, Teng-Hui HUANG
  • Patent number: 10734423
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: August 4, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 10720580
    Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contacts formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 21, 2020
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Publication number: 20200194321
    Abstract: The invention provides a testkey detection circuit, including a plurality of oscillators and a driving circuit. Each of the oscillators has an enable terminal, a voltage terminal and an output terminal, wherein the enable terminals are connected to a common enable terminal. The driving circuit receives the output terminals of the oscillators and increases a driving level of a selected one of the output terminals as a frequency output.
    Type: Application
    Filed: January 16, 2019
    Publication date: June 18, 2020
    Applicant: United Microelectronics Corp.
    Inventors: KUN-YUAN WU, Wei-Jen Wang, Chien-Fu Chen, Chen-Hsien Hsu, Yuan-Hui Chen, Ruei-Yau Chen, Cheng-Tsung Ku, Zhi-Hong Huang, Cheng-Yang Tsai, Yu-Lin Chen
  • Patent number: 10651380
    Abstract: In a non-limiting embodiment, a device may be formed having a substrate that has at least a first region. A base dielectric layer is arranged over the substrate. The base dielectric layer includes an interconnect in the first region. A first electrode is arranged over the interconnect in the first region. A mask structure is arranged over the first electrode. At least one spacer stack is arranged at least partially around the mask structure and the first electrode. The spacer stack(s) includes a resistive switching element at least partially lining sidewalls of the mask structure and the first electrode, and a second electrode arranged over the resistive switching element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 12, 2020
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Yi Jiang, Juan Boon Tan
  • Publication number: 20200127197
    Abstract: A device including a reduced top RRAM electrode structure, and method of production thereof. Embodiments include a bottom resistive random-access memory (RRAM) electrode structure over a plurality of lower metal level contact formed laterally separated in a substrate; a resistive switching structure over the bottom RRAM electrode structure; a top RRAM electrode structure over the resistive switching structure; a protective structure over the top RRAM electrode structure; an encapsulation structure over the bottom RRAM electrode structure and on sidewalls of the resistive switching structure, the top RRAM electrode structure and the protective structure; and an Nblock layer over the substrate.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 23, 2020
    Inventors: Curtis Chun-I HSIEH, Wei-Hui HSU, Wanbing YI, Yi JIANG, Juan Boon TAN
  • Publication number: 20200081503
    Abstract: A hinge structure including a first screw rod, a sliding rod, and a second screw rod is provided. The first screw rod comprises a threaded shaft. The sliding rod is sleeved on the threaded shaft. The second screw rod is sleeved on the sliding rod. The threaded shaft has a first helical slot. The sliding rod has a first guiding portion and a second guiding portion, and the first guiding portion is coupled to the first helical slot. The second screw rod has a second helical slot, and the second guiding portion is coupled to the second helical slot.
    Type: Application
    Filed: November 18, 2019
    Publication date: March 12, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Chih Hsu, Ya-Hui Tseng, Chang-Kai Liu, Ming-Shun Lu, Wen-Jie Hsiao
  • Publication number: 20200066774
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Application
    Filed: November 4, 2019
    Publication date: February 27, 2020
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Patent number: 10520986
    Abstract: A hinge structure including a first screw rod, a sliding rod, and a second screw rod is provided. The first screw rod comprises a threaded shaft. The sliding rod is sleeved on the threaded shaft. The second screw rod is sleeved on the sliding rod. The threaded shaft has a first helical slot. The sliding rod has a first guiding portion and a second guiding portion, and the first guiding portion is coupled to the first helical slot. The second screw rod has a second helical slot, and the second guiding portion is coupled to the second helical slot.
    Type: Grant
    Filed: April 19, 2017
    Date of Patent: December 31, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Wei-Chih Hsu, Ya-Hui Tseng, Chang-Kai Liu, Ming-Shun Lu, Wen-Jie Hsiao
  • Patent number: 10468441
    Abstract: A device including a gate structure formed over a semiconductor substrate, the gate structure having extensions, a device isolation structure formed into the semiconductor substrate adjacent the gate structure, wherein the extensions are over a portion of the device isolation structure, and source/drain regions on both sides of the gate structure, the source/drain regions being formed in a gap in the device isolation structure and being partially enclosed by the extensions of the gate structure.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Min-Feng Kao, Dun-Nian Yaung, Jen-Cheng Liu, Tzu-Hsuan Hsu, Szu-Ying Chen, Wei-Cheng Hsu, Hsiao-Hui Tseng
  • Publication number: 20180175284
    Abstract: Integrated circuits and methods for fabricating integrated circuits with magnetic tunnel junction (MTJ) structures are provided. An exemplary method for fabricating an integrated circuit includes forming an MTJ structure including a top electrode layer. The MTJ structure has a first sidewall and a second sidewall separated from the first sidewall by a first width. The method includes forming a conductive etch stop on the top electrode layer. The conductive etch stop has a second width greater than the first width. The method also includes depositing dielectric material over the conductive etch stop and the MTJ structure. The method further includes etching the dielectric material to form a trench exposing the conductive etch stop. Also, the method includes forming a conductive via in the trench over and in electrical communication with the conductive etch stop.
    Type: Application
    Filed: December 19, 2016
    Publication date: June 21, 2018
    Inventors: Curtis Chun-I Hsieh, Wei-Hui Hsu, Wanbing Yi, Chim Seng Seet, Juan Boon Tan
  • Patent number: 8659869
    Abstract: A method for forming a stacking structure, including forming a ruthenium oxide layer over a substrate; forming a praseodymium oxide layer over the ruthenium oxide layer; and forming a titanium oxide layer over the praseodymium oxide layer; wherein the titanium oxide layer has a rutile phase with the existence of the praseodymium oxide layer underneath. The oxide layers are deposited by a plurality of atomic layer deposition cycles using ruthenium precursor, praseodymium precursor, titanium precursor, and ozone.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: February 25, 2014
    Assignee: Nanya Technology Corporation
    Inventors: Chun I Hsieh, Vishwanath Bhat, Jennifer Sigman, Vassil Antonov, Wei Hui Hsu
  • Publication number: 20130182367
    Abstract: A method for forming a stacking structure, including forming a ruthenium oxide layer over a substrate; forming a praseodymium oxide layer over the ruthenium oxide layer; and forming a titanium oxide layer over the praseodymium oxide layer; wherein the titanium oxide layer has a rutile phase with the existence of the praseodymium oxide layer underneath. The oxide layers are deposited by a plurality of atomic layer deposition cycles using ruthenium precursor, praseodymium precursor, titanium precursor, and ozone.
    Type: Application
    Filed: January 12, 2012
    Publication date: July 18, 2013
    Applicant: Nan Ya Technology Corporation
    Inventors: Chun I HSIEH, Vishwanath Bhat, Jennifer Sigman, Vassil Antonov, Wei Hui Hsu
  • Patent number: 8368134
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Grant
    Filed: April 26, 2010
    Date of Patent: February 5, 2013
    Assignee: Nanya Technology Corporation
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Publication number: 20100200903
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Application
    Filed: April 26, 2010
    Publication date: August 12, 2010
    Applicant: NANYA TECHNOLOGY CORPORATION
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Patent number: 7754614
    Abstract: A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: July 13, 2010
    Assignee: Nanya Technologies Corporation
    Inventors: Ming-Cheng Chang, Chih-Hsiung Hung, Mao-Ying Wang, Wei-Hui Hsu
  • Patent number: D865239
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 29, 2019
    Assignee: CUB ELECPARTS INC.
    Inventors: San-Chuan Yu, Ching-Jui Chuang, Yi-Hui Hsu, Cheng-Hsin Li, Wei-Chang Liang, Chi-Ling Chang, Ya-Ling Chi
  • Patent number: D865273
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 29, 2019
    Assignee: CUB ELECPARTS INC.
    Inventors: San-Chuan Yu, Ching-Jui Chuang, Yi-Hui Hsu, Cheng-Hsin Li, Wei-Chang Liang, Chi-Ling Chang, Ya-Ling Chi
  • Patent number: D865274
    Type: Grant
    Filed: June 18, 2018
    Date of Patent: October 29, 2019
    Assignee: CUB ELECPARTS INC.
    Inventors: San-Chuan Yu, Ching-Jui Chuang, Yi-Hui Hsu, Cheng-Hsin Li, Wei-Chang Liang, Chi-Ling Chang, Ya-Ling Chi