Patents by Inventor Wei-Hung Lin

Wei-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package structure and method for forming the same
    Patent number: 9859229
    Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.
    Type: Grant
    Filed: August 3, 2016
    Date of Patent: January 2, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Peng Tsai, Sheng-Feng Weng, Sheng-Hsiang Chiu, Meng-Tse Chen, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Wafer level chip scale package and method of manufacturing the same
    Patent number: 9837278
    Abstract: A semiconductor structure includes a die including a top surface and a sidewall, and a molding surrounding the die and including a top surface, a sidewall interfacing with the sidewall of the die, and a curved surface including a curvature greater than zero and coupling the sidewall of the molding with the top surface of the molding.
    Type: Grant
    Filed: February 27, 2014
    Date of Patent: December 5, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Hsiang Hu, Wei-Yu Chen, Hung-Jui Kuo, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Advanced INFO POP and Method of Forming Thereof
    Publication number: 20170338202
    Abstract: In accordance with some embodiments, a package-on-package (PoP) structure includes a first semiconductor package having a first side and a second side opposing the first side, a second semiconductor package having a first side and a second side opposing the first side, and a plurality of inter-package connector coupled between the first side of the first semiconductor package and the first side of the second semiconductor package. The PoP structure further includes a first molding material on the second side of the first semiconductor package. The second side of the second semiconductor package is substantially free of the first molding material.
    Type: Application
    Filed: May 17, 2016
    Publication date: November 23, 2017
    Inventors: Yi-Da Tsai, Meng-Tse Chen, Sheng-Feng Weng, Sheng-Hsiang Chiu, Wei-Hung Lin, Ming-Da Cheng, Ching-Hua Hsieh, Chung-Shi Liu
  • Luminous ball
    Patent number: 9821196
    Abstract: A luminous ball is provided, including an internal sphere in which at least one receiving space is disposed; a light-emitting device disposed in the receiving space; at least one covering wrapping an external circumferential surface of the internal sphere; at least one seam formed on an edge of the covering; a plurality of thread apertures disposed in pairs at two sides of the at least one seam; at least one thread penetrating the plurality of thread apertures to stitch the edge of the covering between the two sides of the at least one seam; wherein the internal sphere is a transparent ball, a light generated by the light-emitting device penetrates the internal sphere through the receiving space, and is visible through the at least one seam and the plurality of the thread apertures distributed on the covering.
    Type: Grant
    Filed: August 20, 2016
    Date of Patent: November 21, 2017
    Inventor: Wei-Hung Lin
  • PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170317038
    Abstract: Package structures and methods for forming the same are provided. The package structure includes an integrated circuit die and a first shielding feature over a base layer. The package structure also includes a package layer encapsulating the integrated circuit die and the first shielding feature. The package structure further includes a second shielding feature extending from the side surface of the base layer towards the first shielding feature to electrically connect to the first shielding feature. The side surface of the second shielding feature faces away from the side surface of the base layer and is substantially coplanar with the side surface of the package layer.
    Type: Application
    Filed: August 3, 2016
    Publication date: November 2, 2017
    Inventors: Yu-Peng TSAI, Sheng-Feng WENG, Sheng-Hsiang CHIU, Meng-Tse CHEN, Chih-Wei LIN, Wei-Hung LIN, Ming-Da CHENG, Ching-Hua HSIEH, Chung-Shi LIU
  • Semiconductor packaging structure and method
    Patent number: 9799631
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: October 24, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20170287865
    Abstract: Some embodiments relate to a semiconductor device package, which includes a substrate with a contact pad. A non-solder ball is coupled to the contact pad at a contact pad interface surface. A layer of solder is disposed over an outer surface of the non-solder ball, and has an inner surface and an outer surface which are generally concentric with the outer surface of the non-solder ball. An intermediate layer separates the non-solder ball and the layer of solder. The intermediate layer is distinct in composition from both the non-solder ball and the layer of solder. Sidewalls of the layer of solder are curved or sphere-like and terminate at a planar surface, which is disposed at a maximum height of the layer of solder as measured from the contact pad interface surface.
    Type: Application
    Filed: June 23, 2017
    Publication date: October 5, 2017
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Light releasing sphere structure
    Patent number: 9776048
    Abstract: A modified sphere structure including: a sphere body with a groove formed on a surface of the sphere body along a distribution path; a light source module disposed in a containing space of the sphere body, wherein the groove is connected to the containing space to define a light releasing space and light emitted from the light source passes through the light releasing space; and a light guiding member filling to the light releasing space to allow the light emitted from the light source to be distributed on the light guiding member along the distribution path and transmitted to outside of the sphere body.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: October 3, 2017
    Inventor: Wei-Hung Lin
  • Solder joint structure for ball grid array in wafer level package
    Patent number: 9761551
    Abstract: A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion. The bottom portion is surrounded by a molding compound and the top portion is not surrounded by a molding compound. The method includes depositing and forming a liquid molding compound around an intermediate solder joint using release film, and then etching the molding compound to a reduced height. The resulting solder joint has no waist at the interface of the molding compound and the solder joint. The molding compound has a greater roughness after the etch, greater than about 3 microns, than the molding compound as formed.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: September 12, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Hsiang Hu, Wei-Yu Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Package on package structure and method for forming the same
    Patent number: 9711470
    Abstract: The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • PACKAGE-ON-PACKAGE STRUCTURE HAVING POLYMER-BASED MATERIAL FOR WARPAGE CONTROL
    Publication number: 20170194289
    Abstract: The present disclosure relates to a package-on-package structure providing mechanical strength and warpage control. In some embodiments, the package-on-package structure includes a first set of conductive elements coupling a first package component to a second package component. A first molding material is arranged on the first package component. The first molding material surrounds the first set of conductive elements and outer sidewalls of the second package component and has a top surface below a top surface of the second package component. The stacked integrated chip structure further includes a second set of conductive elements that couples the second package component to a third package component.
    Type: Application
    Filed: March 17, 2017
    Publication date: July 6, 2017
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Semiconductor Packaging Structure and Method
    Publication number: 20170179083
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 22, 2017
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Package on package bonding structure and method for forming the same
    Patent number: 9673182
    Abstract: A method of forming a package on package (PoP) structure includes forming a first die package, and bonding an external connector of a second die package to a solder paste layer of the first die package. The forming the first die package includes forming a contact pad over a substrate, attaching a metal ball with a convex surface to the contact pad, and applying a solder paste layer over a distal end of the metal ball and leaving at least a portion of the metal ball without solder paste. The forming the first die package also includes attaching a semiconductor die to the substrate, and forming a molding compound between the semiconductor die and the metal ball, where the solder paste layer has a first portion extending above an upper surface of the molding compound and a second portion extending below the upper surface of the molding compound.
    Type: Grant
    Filed: July 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Package-on-package structure having polymer-based material for warpage control
    Patent number: 9627355
    Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Flash drive
    Patent number: 9612630
    Abstract: A flash drive including a housing, a carrier, and a storage module is provided. The carrier is movably disposed inside the housing along a first axis. The carrier has an elastic arm being deformable along a second axis. The storage module is assembled to the carrier to move together with the carrier in relative to the housing, so that a connector of the storage module is moved outside the housing or hidden inside the housing. The elastic arm has a contour protruded along a direction away from the storage module when not receiving force.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: April 4, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Wei-Hung Lin
  • Semiconductor Package, Semiconductor Device and Method of Forming the Same
    Publication number: 20170092634
    Abstract: According to an exemplary embodiment, a semiconductor package is provided. The semiconductor package includes at least one chip, and at least one component adjacent to the at least one chip, wherein the at least one chip and the at least one component are molded in a same molding body.
    Type: Application
    Filed: December 9, 2016
    Publication date: March 30, 2017
    Inventors: CHEN-HUA YU, CHUNG-SHI LIU, CHIH-FAN HUANG, TSAI-TSUNG TSAI, WEI-HUNG LIN, MING-DA CHENG
  • Warpage Control in Package-on-Package Structures
    Publication number: 20170084549
    Abstract: A package includes a bottom substrate and a bottom die over and bonded to the bottom substrate. A metal-particle-containing compound material is overlying a top surface of the bottom die, wherein the metal-particle-containing compound material comprises metal particles. A molding material molds at least a lower part of the bottom die therein, wherein the molding material is overlying the bottom substrate.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Wei-Yu Chen, Yu-Hsiang Hu, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • LUMINOUS BALL
    Publication number: 20170065856
    Abstract: A luminous ball is provided, including an internal sphere in which at least one receiving space is disposed; a light-emitting device disposed in the receiving space; at least one covering wrapping an external circumferential surface of the internal sphere; at least one seam formed on an edge of the covering; a plurality of thread apertures disposed in pairs at two sides of the at least one seam; at least one thread penetrating the plurality of thread apertures to stitch the edge of the covering between the two sides of the at least one seam; wherein the internal sphere is a transparent ball, a light generated by the light-emitting device penetrates the internal sphere through the receiving space, and is visible through the at least one seam and the plurality of the thread apertures distributed on the covering.
    Type: Application
    Filed: August 20, 2016
    Publication date: March 9, 2017
    Inventor: Wei-Hung Lin
  • Semiconductor packaging structure and method
    Patent number: 9583464
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Electrical connector
    Patent number: D779438
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 21, 2017
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Hung-I Chung, Wei-Hung Lin