Patents by Inventor Wei-Hung Lin

Wei-Hung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PACKAGE-ON-PACKAGE STRUCTURE HAVING POLYMER-BASED MATERIAL FOR WARPAGE CONTROL
    Publication number: 20160247782
    Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component coupled to a second package component by a first set of conductive elements. A first polymer-comprising material is arranged between the first package component and the second package component. The first polymer-comprising material surrounds the first set of conductive elements and the second package component. A third package component is coupled to the second package component by a second set of conductive elements. An underfill is arranged on the second package component and surrounds the second set of conductive elements. The first polymer-comprising material extends past sidewalls of the underfill.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Alignment in the Packaging of Integrated Circuits
    Publication number: 20160247790
    Abstract: A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.
    Type: Application
    Filed: May 2, 2016
    Publication date: August 25, 2016
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Storage device
    Patent number: 9425569
    Abstract: A storage device includes a base and a storage unit. The base is a conductor of electricity. The storage unit has a first connecting interface and a second connecting interface. The storage unit is disposed on the base, and the base is electrically connected to the first connecting interface or the second connecting interface.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: August 23, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventor: Wei-Hung Lin
  • Substrate and package structure
    Patent number: 9425157
    Abstract: According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.
    Type: Grant
    Filed: February 26, 2014
    Date of Patent: August 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wei-Hung Lin, Hsiu-Jen Lin, Ming-Da Cheng, Yu-Min Liang, Chen-Shien Chen, Chung-Shi Liu
  • Semiconductor packaging structure and method
    Patent number: 9412689
    Abstract: A system and method for packaging semiconductor dies is provided. An embodiment comprises a first package with a first contact and a second contact. A post-contact material is formed on the first contact in order to adjust the height of a joint between the contact pad a conductive bump. In another embodiment a conductive pillar is utilized to control the height of the joint between the contact pad and external connections.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Chung-Shi Liu, Kuei-Wei Huang, Cheng-Ting Chen, Wei-Hung Lin, Ming-Da Cheng
  • Package on-package structures and methods for forming the same
    Patent number: 9412723
    Abstract: A package includes a package component, which further includes a top surface and a metal pad at the top surface of the package component. The package further includes a non-reflowable electrical connector over and bonded to the metal pad, and a molding material over the package component. The non-reflowable electrical connector is molded in the molding material and in contact with the molding material. The non-reflowable electrical connector has a top surface lower than a top surface of the molding compound.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: August 9, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Hsiu-Jen Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Molding structure for wafer level package
    Patent number: 9401337
    Abstract: Apparatus, and methods of manufacture thereof, in which a molding compound is formed between spaced apart microelectronic devices. The molding compound comprises micro-filler elements. No boundary of any of the micro-filler elements is substantially parallel to a substantially planar surface of the molding compound, or to a substantially planar surface of any of the microelectronic devices.
    Type: Grant
    Filed: March 21, 2014
    Date of Patent: July 26, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
  • Package on package bonding structure and method for forming the same
    Patent number: 9397062
    Abstract: The described embodiments of mechanisms of forming a die package and package on package (PoP) structure involve forming a solder paste layer over metal balls of external connectors of a die package. The solder paste layer protects the metal balls from oxidation. In addition, the solder paste layer enables solder to solder bonding with another die package. Further, the solder paste layer moves an intermetallic compound (IMC) layer formed between the solder paste layer and the metal balls below a surface of a molding compound of the die package. Having the IMC layer below the surface strengthens the bonding structure between the two die packages.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: July 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Wei-Yu Chen, Meng-Tse Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Method of manufacturing a semiconductor device
    Patent number: 9385040
    Abstract: A method of manufacturing a semiconductor device includes providing a wafer, grinding a backside of the wafer, disposing a backside film on the backside of the wafer, cutting the wafer to singulate a plurality of dies from the wafer, and forming a mark on the backside film disposed on each of the plurality of dies by a laser operation.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: July 5, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Tsai-Tsung Tsai, Wen-Hsiung Lu, Yu-Peng Tsai, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
    Publication number: 20160190096
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 30, 2016
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Solder Joint Structure for Ball Grid Array in Wafer Level Package
    Publication number: 20160181219
    Abstract: A semiconductor device package and a method for forming the same using an improved solder joint structure are disclosure. The package includes solder joints having a thinner bottom portion than a top portion. The bottom portion is surrounded by a molding compound and the top portion is not surrounded by a molding compound. The method includes depositing and forming a liquid molding compound around an intermediate solder joint using release film, and then etching the molding compound to a reduced height. The resulting solder joint has no waist at the interface of the molding compound and the solder joint. The molding compound has a greater roughness after the etch, greater than about 3 microns, than the molding compound as formed.
    Type: Application
    Filed: February 15, 2016
    Publication date: June 23, 2016
    Inventors: Yu-Hsiang Hu, Wei-Yu Chen, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Package structures and methods for forming the same
    Patent number: 9362236
    Abstract: A packaging structure and a method of forming a packaging structure are provided. The packaging structure, such as an interposer, is formed by optionally bonding two carrier substrates together and simultaneously processing two carrier substrates. The processing includes forming a sacrificial layer over the carrier substrates. Openings are formed in the sacrificial layers and pillars are formed in the openings. Substrates are attached to the sacrificial layer. Redistribution lines may be formed on an opposing side of the substrates and vias may be formed to provide electrical contacts to the pillars. A debond process may be performed to separate the carrier substrates. Integrated circuit dies may be attached to one side of the redistribution lines and the sacrificial layer is removed.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Liang Meng, Wei-Hung Lin, Jimmy Liang, Ming-Che Ho, Hung-Jui Kuo, Chung-Shi Liu, Mirng-Ji Lii
  • Package-on-package structure having polymer-based material for warpage control
    Patent number: 9349663
    Abstract: A package on package structure providing mechanical strength and warpage control includes a first package component, a second package component, and a first set of conductive elements coupling the first package component to the second package component. A first polymer-comprising material is molded on the first package component and surrounds the first set of conductive elements. The first polymer-comprising material has an opening therein exposing a top surface of the second package component. A third package component and a second set of conductive elements couples the second package component to the third package component.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Tse Chen, Yu-Chih Liu, Hui-Min Huang, Wei-Hung Lin, Jing Ruei Lu, Ming-Da Cheng, Chung-Shi Liu
  • Alignment in the packaging of integrated circuits
    Patent number: 9343386
    Abstract: A method includes aligning a top package to a bottom package using an alignment mark in the bottom package, and placing the top package over the bottom package, wherein the top package is aligned to the bottom package after the placing the top package over the bottom package. A reflow is then performed to bond the top package to the bottom package.
    Type: Grant
    Filed: June 19, 2013
    Date of Patent: May 17, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuei-Wei Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices
    Publication number: 20160133538
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die.
    Type: Application
    Filed: January 14, 2016
    Publication date: May 12, 2016
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Chih-Wei Lin, Wei-Hung Lin, Ming-Da Cheng
  • Device packaging
    Patent number: 9331023
    Abstract: Some embodiments of the present disclosure provide a semiconductive device, including a semiconductive substrate. A conductive pad is on the semiconductive substrate. A passivation layer covers the conductive pad and overlies the semiconductive substrate. A first protective layer overlies the passivation layer. The first protective layer includes an opening exposing a portion of the passivation layer, and the opening includes at least two lines in contact with each other. A post passivation interconnect (PPI) layer overlies the first protective layer. A conductor forms on the PPI layer.
    Type: Grant
    Filed: November 28, 2014
    Date of Patent: May 3, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ming-Kai Liu, Yu-Peng Tsai, Kai-Chiang Wu, Wei-Hung Lin, Hao-Yi Tsai, Mirng-Ji Lii
  • PACKAGE ON PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20160111385
    Abstract: The described embodiments of mechanisms of forming a package on package (PoP) structure involve bonding with connectors with non-solder metal balls to a packaging substrate. The non-solder metal balls may include a solder coating layer. The connectors with non-solder metal balls can maintain substantially the shape of the connectors and control the height of the bonding structures between upper and lower packages. The connectors with non-solder metal balls are also less likely to result in bridging between connectors or disconnection (or cold joint) of bonded connectors. As a result, the pitch of the connectors with non-solder metal balls can be kept small.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 21, 2016
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Ming-Da Cheng, Mirng-Ji Lii, Meng-Tse Chen, Wei-Hung Lin
  • Packaged semiconductor devices and methods of packaging semiconductor devices
    Patent number: 9299688
    Abstract: Packaged semiconductor devices and methods of packaging semiconductor devices are disclosed. In some embodiments, a method of packaging a semiconductor device includes forming a mask coating over a carrier, coupling an integrated circuit die over the mask coating, and disposing a molding compound around the integrated circuit die. The method includes forming an interconnect structure over the integrated circuit die and the molding compound.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: March 29, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Fan Huang, Hui-Min Huang, Wei-Hung Lin, Ming-Da Cheng
  • Connector and storage device using the same
    Patent number: 9281631
    Abstract: A connector suitable for a storage device is provided. The storage device has a storage module. The connector includes a body, a plurality of terminals, and a housing. The terminals are disposed in the body, and a first end of each terminal protrudes from the body and is electrically connected to the storage module. The housing covers the body and has an indentation and a shielding portion. The first end of each terminal is located at the indentation. The shielding portion shields the indentation, and the first end of each terminal is located between the shielding portion and the storage module. A storage device is also provided.
    Type: Grant
    Filed: May 19, 2014
    Date of Patent: March 8, 2016
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Wei-Hung Lin, Hsien-Sheng Tsao, Yun-Chieh Chen
  • Packaging methods and packaged semiconductor devices
    Patent number: 9269687
    Abstract: Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Yu-Peng Tsai, Chun-Cheng Lin, Chih-Wei Lin, Ming-Da Cheng, Chung-Shi Liu