Abstract: Embodiments of copper-free semiconductor device interfaces and methods for forming and/or utilizing the same are provided herein. In some embodiments, a semiconductor structure may include a substrate having an exposed copper-containing feature; and a copper-free interface disposed over the substrate and providing a conductive interconnect between the copper-containing feature and an upper surface of the copper-free interface to facilitate electrical coupling of the substrate to a semiconductor device while physically isolating the semiconductor device from the copper-containing feature.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group III metal.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.

Abstract: An improvement to a method of fabricating an integrated circuit. All dielectric material that is laterally surrounding an electrically conductive interconnect is removed, while leaving the dielectric material that directly underlies the electrically conductive interconnect. The electrically conductive interconnect is back filled with a low k material, where the low k material provides low capacitance between laterally adjacent electrically conductive interconnects, and the remaining dielectric material underlying the electrically conductive interconnects provides structural support to the electrically conductive interconnects.

Abstract: An improvement to a method of forming an integrated circuit. An etch stop layer is formed to overlie the front end processing layers of the integrated circuit. Support structures are formed that are disposed so as to support electrically conductive interconnects on various levels of the integrated circuit. Substantially all of the non electrically conductive layers above the etch stop layer that were formed during the fabrication of the interconnects are removed.

Abstract: A process for forming an integrated circuit structure comprises forming a layer of low k dielectric material over a previously formed integrated circuit structure, and treating the upper surface of the layer of low k dielectric material with a plasma to form a layer of densified dielectric material over the remainder of the underlying layer of low k dielectric material, forming a second layer of low k dielectric material over the layer of densified dielectric material, and treating this second layer of low k dielectric material to form a second layer of densified dielectric material over the second layer of low k dielectric material. The layer or layers of densified dielectric material formed from the low k dielectric material provide mechanical support and can then function as etch stop and mask layers for the formation of vias and/or trenches.

Abstract: The present invention provides a method of forming a high-k dielectric layer on a semiconductor wafer. A metal silicate dielectric layer is initially deposited on the wafer. A dopant having dissociable oxygen is introduced into the metal silicate on the wafer. According to one embodiment the metal silicate comprises a group IV metal and the dopant is an oxide of one of an alkaline metal and an alkaline earth metal. According to another embodiment the metal silicate comprises a group IV metal.

Abstract: A three step process for planarizing an integrated circuit structure comprising one or more dielectric layers having trench and/or via openings therein lined with a layer of electrically conductive barrier liner material and filled with copper filler material. Sufficient excess copper (formed over the barrier liner portions on the top surface of the dielectric layer) is removed in an initial chemical mechanical polish (CMP) step to provide a planarized copper layer with a global planarity of about 20 nm to about 30 nm. The remainder of the excess copper over the portion of the barrier liner material lying on the top surface of the dielectric layer is then removed by electropolishing the structure, in a second step, until all of the excess copper over the portion of the barrier liner material lying on the top surface of the dielectric layer is removed.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: A method of forming a planarized layer on a substrate, where the substrate is cleaned, and the layer is formed having a surface with high portions and low portions. A resistive mask is formed over the low portions of the layer, but not over the high portions of the layer. The surface of the layer is etched, where the high portions of the layer are exposed to the etch, but the low portions of the layer underlying the resistive mask are not exposed to the etch. The etch of the surface of the layer is continued until the high portions of the layer are at substantially the same level as the low portions of the layer, thereby providing an initial planarization of the surface of the layer. The resistive mask is removed from the surface of the layer, and all of the surface of the layer is planarized to provide a planarized layer.