Abstract: The invention comprises a process for forming a dielectric film having a compressive stress exhibited in the layers deposited onto an integrated circuit structure. This process includes depositing a first thin layer of dielectric material onto an integrated circuit structure, then exposing the integrated circuit structure to an elevated temperature. Then a second thin layer of dielectric material is deposited immediately overtop of the first thin layer of dielectric material, and then the integrated circuit structure is again exposed to an elevated temperature. The process is carried out to insure that the composite layer comprising the first and second deposited thin dielectric layers, after heat treatment, exhibits a residual stress which is compressive.

Abstract: A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.

Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

Abstract: A process for forming low k silicon oxide dielectric material having a dielectric constant no greater than 3.0, while suppressing pressure spikes during the formation of the low k silicon oxide dielectric material comprises reacting an organo-silane and hydrogen peroxide in a reactor chamber containing a silicon substrate while maintaining an electrical bias on the substrate. In a preferred embodiment the reactants are flowed into the reactor at a reactant flow ratio of organo-silane reactant to hydrogen peroxide reactant of not more than 10.6 sccm of organo-silane reactant per 0.1 grams/minute of hydrogen peroxide reactant; and the substrate is biased with either a positive DC bias potential, with respect to the grounded reactor chamber walls, of about +50 to +300 volts, or a low frequency AC bias potential ranging from a minimum of +50/-50 volts up to a maximum of about +300/-300 volts.

Abstract: A method for treating exposed surfaces of a low k carbon doped silicon oxide dielectric material in order to protect the low k carbon doped silicon oxide dielectric material from damage during removal of photoresist mask materials is described. The process comprises (a) first treating the exposed surfaces of a low k carbon doped silicon oxide dielectric material with a plasma capable of forming a densified layer on and adjacent the exposed surfaces of low k carbon doped silicon oxide dielectric material and (b) then treating the semiconductor wafer with a mild oxidizing agent capable of removing photoresist materials from the semiconductor wafer. These steps will prevent the degradation of the exposed surfaces of a low k carbon doped silicon oxide dielectric material during removal of an etch mask after formation of vias or contact openings in the low k carbon doped silicon oxide dielectric material.

Abstract: Provided is a method and composition for RF sputter cleaning of contact and via holes which provides substantially uniform charge distribution in the holes and minimizes electron shadowing. This is accomplished by isotropically depositing, such as by PVD, a layer of conductive material at the wafer surface surrounding a hole and down the sides of the hole. Isotropic deposition is such that in high aspect ratio trenches and holes deposition is heaviest at the top and minimal at the bottom (due to the deposition shadowing effect). The deposited conductive material is preferably a metal that is also used as a liner in the holes prior to depositing the plug material. The conductive material provides path for negative charge otherwise accumulating at the top of a hole during RF sputter cleaning to reach the bottom of the hole and thereby prevents accumulations of charge of one polarity in and around the hole. Thus, the stress on the gate oxide caused by conventional RF sputtering, described above, is relieved.

Abstract: A method of forming titanium nitride barrier layers that are highly conformal, have high step coverage and low resistivity through a two stage deposition process is described. Low temperature deposition of titanium nitride barrier layer provides material of high conformity and good step coverage but of high resistivity. High temperature deposition of titanium nitride barrier layer yields material of low resistivity. Thus, a titanium nitride barrier layer deposited in separate steps at low temperature and high temperature by the method of the present invention is particularly suited for use in modern devices of increasing density that are characterized by narrow and deep contact holes.

Abstract: A process and apparatus are described for inhibiting, but not completely eliminating, the deposition of titanium nitride by MOCVD on the end edge of a semiconductor substrate which comprises directing toward such substrate end edge a flow of one or more deposition-inhibiting gases in a direction which substantially opposes the flow of process gases toward the end edges of the substrate. This flow of deposition-inhibiting gases toward the end edges of the substrate reduces the deposition of the titanium nitride at the end edge of the semiconductor substrate either by directing some of the flow of process gases away from such end edge of the substrate, or by locally diluting such process gases in the region of the deposition chamber adjacent the end edge of the substrate, or by some combination of the foregoing.

Abstract: A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.

Abstract: A method is provided for the controlled formation of voids in integrated circuit doped glass dielectric films. The film can be formed of borophosphosilica glass (BPSG) or other types of doped glass. The method involves the steps of providing a substrate on which conductors are formed, depositing a first layer of doped glass to a thickness in a predetermined ratio to the size of the space between conductors, reflowing the first doped glass layer, applying one or more additional doped glass layers to make up for any shortfall in desired total doped glass thickness, and performing a high temperature densification to smooth each additional layer. The method provides for increased integrated circuit speed by controlled formation of voids which have a low dielectric constant and therefore reduce capacitance between adjacent conductors. The method can be performed using existing doped glass deposition and reflow equipment.