Patents by Inventor Wei Jen Lo
Wei Jen Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250022957Abstract: The present disclosure provides a semiconductor device and a method of forming the same. A method according one embodiment of the present disclosure include forming a stack over a substrate, forming a fin-shape structure from patterning the stack and the substrate, recessing the fin-shape structure to form a source/drain trench, depositing a dielectric film in the source/drain trench with a top surface below a top surface of the substrate in the fin-shape structure, and forming an epitaxial feature over the dielectric film. A bottom surface of the epitaxial feature is below the top surface of the substrate in the fin-shape structure.Type: ApplicationFiled: October 23, 2023Publication date: January 16, 2025Inventors: Che-Yu Lin, Chien-Chia Cheng, Chih-Chiang Chang, Chien-I Kuo, Ming-Hua Yu, Chii-Horng Li, Syun-Ming Jang, Wei-Jen Lo
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Patent number: 12176251Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.Type: GrantFiled: July 25, 2023Date of Patent: December 24, 2024Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
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Publication number: 20240413020Abstract: A method includes forming a contact spacer on a sidewall of an inter-layer dielectric, wherein the contact spacer encircles a contact opening, forming a silicide region in the opening and on a source/drain region, depositing an adhesion layer extending into the contact opening, and performing a treatment process, so that the contact spacer is treated. The treatment process is selected from the group consisting of an oxidation process, a carbonation process, and combinations thereof. The method further includes depositing a metal barrier over the adhesion layer, depositing a metallic material to fill the contact opening, and performing a planarization process to remove excess portions of the metallic material over the inter-layer dielectric.Type: ApplicationFiled: October 17, 2023Publication date: December 12, 2024Inventors: Min-Hsiu Hung, Chun-I Tsai, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo, Wei-Jung Lin, Yu-Ting Wen, Kai-Chieh Yang
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Publication number: 20240413215Abstract: A method includes forming a stack of layers, which includes a plurality of semiconductor nanostructures, and a plurality of sacrificial layers. The plurality of semiconductor nanostructures and the plurality of sacrificial layers are arranged alternatingly. The method further includes laterally recessing the plurality of sacrificial layers to form lateral recesses, depositing a spacer layer extending into the lateral recesses, trimming the spacer layer to form inner spacers, and performing a treatment process to reduce dielectric constant values of the inner spacers.Type: ApplicationFiled: August 18, 2023Publication date: December 12, 2024Inventors: Wei-Jen Lo, Syun-Ming Jang, Mu-Chieh Chang, Tze-Liang Lee
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Publication number: 20240363353Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate; forming a source/drain region over the fin adjacent to the gate structure; forming an interlayer dielectric (ILD) layer over the source/drain region around the gate structure; forming an opening in the ILD layer to expose the source/drain region; forming a silicide region and a barrier layer successively in the openings over the source/drain region, where the barrier layer includes silicon nitride; reducing a concentration of silicon nitride in a surface portion of the barrier layer exposed to the opening; after the reducing, forming a seed layer on the barrier layer; and forming an electrically conductive material on the seed layer to fill the opening.Type: ApplicationFiled: August 14, 2023Publication date: October 31, 2024Inventors: Pin-Wen Chen, Yu-Chen Ko, Chi-Yuan Chen, Ya-Yi Cheng, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
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Publication number: 20240355663Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.Type: ApplicationFiled: June 28, 2024Publication date: October 24, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Chi LIN, Huai-Tei YANG, Lun-Kuang TAN, Wei-Jen LO, Chih-Teng LIAO
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Publication number: 20240355740Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.Type: ApplicationFiled: June 30, 2023Publication date: October 24, 2024Inventors: Feng-Yu Chang, Sheng-Hsuan Lin, Shu-Lan Chang, Kai-Yi Chu, Meng-Hsien Lin, Pei-Hsuan Lee, Pei Shan Chang, Chih-Chien Chi, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
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Publication number: 20240332068Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.Type: ApplicationFiled: June 10, 2024Publication date: October 3, 2024Inventors: Wei-Jen Lo, Po-Cheng Shih, Syun-Ming Jang, Tze-Liang Lee
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Publication number: 20240332018Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.Type: ApplicationFiled: June 10, 2024Publication date: October 3, 2024Inventors: Chih Yung HUNG, Wei-Jen LO, Cheng-Han LEE, Ching-Lun LAI, Chien-Feng LIN, Shahaji B. MORE, Shih-Chieh CHANG
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Patent number: 12080582Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.Type: GrantFiled: January 10, 2022Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Chi Lin, Huai-Tei Yang, Lun-Kuang Tan, Wei-Jen Lo, Chih-Teng Liao
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Publication number: 20240274555Abstract: Embodiments provide a method and resulting structure that includes forming an opening in a dielectric layer to expose a metal feature, selectively depositing a metal cap on the metal feature, depositing a barrier layer over the metal cap, and depositing a conductive fill on the barrier layer.Type: ApplicationFiled: May 8, 2023Publication date: August 15, 2024Inventors: Wei-Jen Lo, Syun-Ming Jang, Ming-Hsing Tsai, Chun-Chieh Lin, Hung-Wen Su, Ya-Lien Lee, Chih-Han Tseng, Chih-Cheng Kuo, Yi-An Lai, Kevin Huang, Kuan-Hung Ho
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Patent number: 12033890Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.Type: GrantFiled: April 28, 2023Date of Patent: July 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Jen Lo, Po-Cheng Shih, Syun-Ming Jang, Tze-Liang Lee
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Patent number: 12009208Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.Type: GrantFiled: December 8, 2021Date of Patent: June 11, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih Yung Hung, Shahaji B. More, Chien-Feng Lin, Cheng-Han Lee, Shih-Chieh Chang, Ching-Lun Lai, Wei-Jen Lo
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Publication number: 20230369132Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Da-Yuan LEE, Hung-Chin CHUNG, Hsien-Ming LEE, Kuan-Ting LIU, Syun-Ming JANG, Weng CHANG, Wei-Jen LO
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Patent number: 11804409Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.Type: GrantFiled: July 26, 2021Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Da-Yuan Lee, Hung-Chin Chung, Hsien-Ming Lee, Kuan-Ting Liu, Syun-Ming Jang, Weng Chang, Wei-Jen Lo
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Publication number: 20230268224Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.Type: ApplicationFiled: April 28, 2023Publication date: August 24, 2023Inventors: Wei-Jen Lo, Po-Cheng Shih, Syun-Ming Jang, Tze-Liang Lee
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Patent number: 11676855Abstract: A representative method includes forming a photo-sensitive material over a substrate, and forming a cap layer over the photo-sensitive material, and patterning the cap layer. Using the patterned cap layer, a first portion of the photo-sensitive material is selectively exposed to a pre-selected light wavelength to change at least one material property of the first portion of the photo-sensitive material, while preventing a second portion of the photo-sensitive material from being exposed to the pre-selected light wavelength. One, but not both of the following steps is then conducted: removing the first portion of the photo-sensitive material and forming in its place a conductive element at least partially surrounded by the second portion of the photo-sensitive material, or removing the second portion of the photo-sensitive material and forming from the first portion of the photo-sensitive material a conductive element electrically connecting two or more portions of a circuit.Type: GrantFiled: November 10, 2020Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Jen Lo, Po-Cheng Shih, Syun-Ming Jang, Tze-Liang Lee
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Publication number: 20220392767Abstract: The present disclosure provides a semiconductor processing apparatus according to one embodiment. The semiconductor processing apparatus includes a chamber; a base station located in the chamber for supporting a semiconductor substrate; a preheating assembly surrounding the base station; a first heating element fixed relative to the base station and configured to direct heat to the semiconductor substrate; and a second heating element moveable relative to the base station and operable to direct heat to a portion of the semiconductor substrate.Type: ApplicationFiled: December 8, 2021Publication date: December 8, 2022Inventors: Chih Yung Hung, Shahaji B. More, Chien-Feng Lin, Cheng-Han Lee, Shih-Chieh Chang, Ching-Lun Lai, Wei-Jen Lo
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Publication number: 20220238337Abstract: A method includes placing a wafer into a production chamber, providing a heating source to heat the wafer, and projecting a laser beam on the wafer using a laser projector. The method further includes, when the wafer is heated by both of the heating source and the laser beam, performing a process selected from an epitaxy process to grow a semiconductor layer on the wafer, and an etching process to etch the semiconductor layer.Type: ApplicationFiled: December 6, 2021Publication date: July 28, 2022Inventors: Yee-Chia Yeo, Syun-Ming Jang, Wei-Jen Lo
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Publication number: 20220130706Abstract: A method for cleaning debris and contamination from an etching apparatus is provided. The etching apparatus includes a process chamber, a source of radio frequency power, an electrostatic chuck within the process chamber, a chuck electrode, and a source of DC power connected to the chuck electrode. The method of cleaning includes placing a substrate on a surface of the electrostatic chuck, applying a plasma to the substrate, thereby creating a positively charged surface on the surface of the substrate, applying a negative voltage or a radio frequency pulse to the electrode chuck, thereby making debris particles and/or contaminants from the surface of the electrostatic chuck negatively charged and causing them to attach to the positively charged surface of the substrate, and removing the substrate from the etching apparatus thereby removing the debris particles and/or contaminants from the etching apparatus.Type: ApplicationFiled: January 10, 2022Publication date: April 28, 2022Inventors: Yu-Chi LIN, Huai-Tei YANG, Lun-Kuang TAN, Wei-Jen LO, Chih-Teng LIAO