Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

Abstract: A feeding mold is provided with a charging runner for coating, a feeding runner connected to the charging runner, and a mold base adjacent to the feeding runner. The feeding runner is provided with a splitting manifold communicated with the charging runner, a discharging end face located at the end of feeding runner and apart from an atomizing knife edge of ultrasonic oscillating element by a gap, and a slit channel connected to the splitting manifold and discharging end face. The mold base is connected at a side edge thereof to the bottom of discharging end face, and inclined at a first angle toward the discharging end face. The side edge is located at the lowest position. Accordingly, the backflow of coating on the discharging end face to the mold base from the side edge and formation of trickle are impossible, so as to use coating adequately and avoid pollution.

Abstract: A method for fabricating a pellicle includes forming a first dielectric layer over a back surface of a substrate. After forming the first dielectric layer, and in some embodiments, a graphene layer is formed over a front surface of the substrate. In some examples, after forming the graphene layer, the first dielectric layer is patterned to form an opening in the first dielectric layer that exposes a portion of the back surface of the substrate. Thereafter, while using the patterned first dielectric layer as a mask, an etching process may be performed to the back surface of the substrate to form a pellicle having a pellicle membrane that includes the graphene layer.

Abstract: A touch sensing device including a substrate, a plurality of first sensing series separated from each other and a plurality of second sensing series separated from each other is provided. The substrate has a first surface and a second surface. The first sensing series are disposed on the first surface. Each of the first sensing series includes a plurality of first sensing pads connected to each other. The second sensing series are disposed on the first surface. Each of the second sensing series includes a plurality of second sensing pads distributed between the first sensing series and a plurality of connection lines connecting the second sensing pads. Each of the connection lines extends along an edge of one of the first sensing series, and each of the connection lines is electrically connected to the second sensing pads located at two opposite sides of the first sensing series.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function metal layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: A touch sensing device including a substrate, a plurality of first sensing series separated from each other and a plurality of second sensing series separated from each other is provided. The substrate has a first surface and a second surface. The first sensing series are disposed on the first surface. Each of the first sensing series includes a plurality of first sensing pads connected to each other. The second sensing series are disposed on the first surface. Each of the second sensing series includes a plurality of second sensing pads distributed between the first sensing series and a plurality of connection lines connecting the second sensing pads. Each of the connection lines extends along an edge of one of the first sensing series, and each of the connection lines is electrically connected to the second sensing pads located at two opposite sides of the first sensing series.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function meta layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: A clock generating device is disclosed. The clock generating device includes a clock generating unit, for counting a synchronization period of a synchronization signal, generating a first interrupt signal according to the synchronization signal, generating a pulse-width modulation signal according a control signal, counting a phase difference between the synchronization signal and the pulse-width modulation signal, and generating a second interrupt signal according to the pulse-width modulation signal; and a computing unit, for acquiring the synchronization period according to the first interrupt signal, acquiring the phase difference according to the second interrupt signal, and adjusting the control signal according to the synchronization period, a modulation period of the pulse-width modulation signal and the phase difference.

Abstract: An embodiment wafer polishing tool includes an abrasive tape, a polish head holding the abrasive tape, and a rotation module. The rotation module is configured to rotate a wafer during a wafer polishing process, and the polish head is configured to apply pressure to the abrasive tape toward a first surface of the wafer during the wafer polishing process.

Abstract: A clock generating device is disclosed. The clock generating device includes a clock generating unit, for counting a synchronization period of a synchronization signal, generating a first interrupt signal according to the synchronization signal, generating a pulse-width modulation signal according a control signal, counting a phase difference between the synchronization signal and the pulse-width modulation signal, and generating a second interrupt signal according to the pulse-width modulation signal; and a computing unit, for acquiring the synchronization period according to the first interrupt signal, acquiring the phase difference according to the second interrupt signal, and adjusting the control signal according to the synchronization period, a modulation period of the pulse-width modulation signal and the phase difference.

Abstract: An ultrasonic spray coating system includes a piezoelectric transducer, a spray-forming head and a liquid supply applicator. The spray-forming head has an air-entrainment mechanism. The air-entrainment mechanism has an air-stream channel that is formed inside a main body and a bottom body of the spray-forming head for connection with a high-pressure air source, and an air vent formed in a bottom surface of the bottom body and communicates with the air-stream channel. A length of the air vent in a horizontal direction is greater than that of the air-stream channel. The liquid supply applicator has a discharge orifice, and a control component for controlling the size of the discharge orifice.

Abstract: The present disclosure provides a semiconductor device with a profiled work-function metal gate electrode. The semiconductor structure includes a metal gate structure formed in an opening of an insulating layer. The metal gate structure includes a gate dielectric layer, a barrier layer, a work-function meta layer between the gate dielectric layer and the barrier layer and a work-function adjustment layer over the barrier layer, wherein the work-function metal has an ordered grain orientation. The present disclosure also provides a method of making a semiconductor device with a profiled work-function metal gate electrode.

Abstract: An image processing method for processing an input image is provided. The image processing method includes: performing a plurality of first imaging processing operations on the input image to generate a first image; and performing a plurality of second imaging processing operations on the first image. Each of the first imaging processing operations is along a first direction, and the plurality of first imaging processing operations include a first scaling operation for increasing resolution. Each of the second imaging processing operations is along a second direction different from the first direction, and the plurality of second imaging processing operations include a second scaling operation for increasing resolution.

Abstract: An image processing method for processing an input image is provided. The image processing method includes: performing a plurality of first imaging processing operations on the input image to generate a first image; and performing a plurality of second imaging processing operations on the first image. Each of the first imaging processing operations is along a first direction, and the plurality of first imaging processing operations include a first scaling operation for increasing resolution. Each of the second imaging processing operations is along a second direction different from the first direction, and the plurality of second imaging processing operations include a second scaling operation for increasing resolution.

Abstract: An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, one or more line buffers, a first sharpness circuit, a second scaling circuit, and a second sharpness circuit. The first scaling circuit enlarges an input image along a first direction to generate a first enlarged image. The one or more line buffers temporarily store the pixel values of a plurality of pixel rows of the first enlarged image. The first sharpness circuit vertically sharpens the first enlarged image to generate a first sharpened image. The second scaling circuit enlarges the first sharpened image along a second direction to generate a second enlarged image. The second sharpness circuit horizontally sharpens the second enlarged image to generate a second sharpened image. Accordingly, it is possible to use the one or more line buffers having shorter data lengths to perform the vertical sharpening.

Abstract: An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, one or more line buffers, a first sharpness circuit, a second scaling circuit, and a second sharpness circuit. The first scaling circuit enlarges an input image along a first direction to generate a first enlarged image. The one or more line buffers temporarily store the pixel values of a plurality of pixel rows of the first enlarged image. The first sharpness circuit vertically sharpens the first enlarged image to generate a first sharpened image. The second scaling circuit enlarges the first sharpened image along a second direction to generate a second enlarged image. The second sharpness circuit horizontally sharpens the second enlarged image to generate a second sharpened image. Accordingly, it is possible to use the one or more line buffers having shorter data lengths to perform the vertical sharpening.

Abstract: An image processing circuit and a method thereof are provided herein. The image processing circuit has a first scaling circuit, a plurality of line buffers, a first sharpness circuit, a second scaling circuit, and a second sharpness circuit. The first scaling circuit enlarges an input image along a first direction to generate a first enlarged image. The line buffers temporarily store the pixel values of a plurality of pixel rows of the first enlarged image. The first sharpness circuit vertically sharpens the first enlarged image to generate a first sharpened image. The second scaling circuit enlarges the first sharpened image along a second direction to generate a second enlarged image. The second sharpness circuit horizontally sharpens the second enlarged image to generate a second sharpened image. Accordingly, it is possible to use the line buffers having shorter data lengths to perform the vertical sharpening.