Patents by Inventor Wei-jer Hsieh
Wei-jer Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240201232Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.Type: ApplicationFiled: February 26, 2024Publication date: June 20, 2024Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
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Publication number: 20240161822Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: ApplicationFiled: January 19, 2024Publication date: May 16, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Patent number: 11913980Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.Type: GrantFiled: March 6, 2023Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
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Patent number: 11915746Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: GrantFiled: May 12, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Publication number: 20230326505Abstract: A memory device including a first memory cell, a first tracking cell, a tracking bit line, a second tracking cell and a word line driver. The first memory cell is configured to receive a first word line signal. The first tracking cell is configured to emulate the first memory cell. The tracking bit line is configured to transmit a tracking bit line signal to the first tracking cell. The second tracking cell is configured to adjust the tracking bit line signal according to the first word line signal. The word line driver is configured to adjust the first word line signal according to the tracking bit line signal and a first distance between the second tracking cell and a common node on the tracking bit line.Type: ApplicationFiled: June 16, 2023Publication date: October 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien HUANG, Wei-Jer HSIEH, Yu-Hao HSU
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Publication number: 20230298657Abstract: A power control device includes a first switch and a second switch. A first terminal of the first switch is configured to receive a first voltage signal in a first voltage domain, and a first terminal of the second switch is configured to receive a second voltage signal in a second voltage domain different from the a first voltage domain. A second terminal of the second switch is coupled to a second terminal of the first switch, and a control circuit is coupled to control terminals of the first switch and the second switch. The control circuit is configured to turn on the first switch in response to a decrease of a voltage level of the first voltage signal.Type: ApplicationFiled: June 3, 2022Publication date: September 21, 2023Inventors: Zhi-Hao Chang, Wei-jer Hsieh, Yangsyu Lin
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Publication number: 20230260571Abstract: The present disclosure provides a memory circuit. The memory circuit includes: a plurality of word lines, a word line driver, and a first conductive line. The word line driver is electrically connected to the word lines. The word line driver includes: a plurality of first electronic components and a plurality of second electronic components. The plurality of first electronic components each electrically connected to the corresponding word line. The plurality of second electronic components each having a first terminal and a second terminal. The first terminal is electrically connected to the corresponding word line and the corresponding first electronic component. The first conductive line is electrically connected to the second terminal of the second electronic components. The first conductive line has a length proportional to the number of the word lines.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Inventors: ZHI-HAO CHANG, WEI-JER HSIEH
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Patent number: 11727972Abstract: A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.Type: GrantFiled: August 27, 2021Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien Huang, Wei-Jer Hsieh, Yu-Hao Hsu
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Publication number: 20230204634Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
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Patent number: 11598794Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.Type: GrantFiled: July 22, 2020Date of Patent: March 7, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
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Publication number: 20230064595Abstract: A memory device is disclosed. The memory device includes word lines, a tracking bit line and a word line driver. The word lines are configured to transmit word line signals to memory cells. The tracking bit line is coupled to a first plurality of tracking cells that are arranged in rows. The word line driver is coupled to the word lines and a control circuit that is coupled through the tracking bit line to the word lines. The word line driver is configured to control a falling edge of each of the word line signals, by receiving each corresponding tracking bit line signal of tracking bit line signals transmitted from the tracking bit line, based on a resistance of a length of the tracking bit line. The length is substantially distanced from each corresponding row of the rows to the control circuit. A method is also disclosed herein.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Tsung-Hsien HUANG, Wei-Jer HSIEH, Yu-Hao HSU
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Publication number: 20230041094Abstract: A memory device and a method of operating the memory device are disclosed. In one aspect, the memory device includes a word line driver connected to a word line, a row of memory cells connected to the word line, each memory cell powered by a first supply voltage, and a power circuit. The power circuit is configured to provide the first supply voltage to the word line driver when a read condition is satisfied, and a second supply voltage to the word line driver when the read condition is not satisfied, the second supply voltage being less than the first supply voltage.Type: ApplicationFiled: February 11, 2022Publication date: February 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Hsien Huang, Wei-jer Hsieh, Tsung-Yuan Huang, Yu-Hao Hsu
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Publication number: 20220328097Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.Type: ApplicationFiled: June 27, 2022Publication date: October 13, 2022Inventors: Wei-jer Hsieh, Chiting Cheng, Yangsyu Lin, Shang-Chi Wu
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Publication number: 20220270674Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: ApplicationFiled: May 12, 2022Publication date: August 25, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Patent number: 11373702Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.Type: GrantFiled: October 24, 2019Date of Patent: June 28, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Jer Hsieh, Chiting Cheng, Yangsyu Lin, Shang-Chi Wu
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Patent number: 11355183Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: GrantFiled: August 25, 2020Date of Patent: June 7, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Publication number: 20220068372Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.Type: ApplicationFiled: August 25, 2020Publication date: March 3, 2022Inventors: Wei-jer Hsieh, Yu-Hao Hsu, Zhi-Hao Chang, Cheng Hung Lee
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Publication number: 20220026475Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.Type: ApplicationFiled: July 22, 2020Publication date: January 27, 2022Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
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Patent number: 11087833Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.Type: GrantFiled: June 22, 2020Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chen Kuo, Cheng-Hung Lee, Chi-Ting Cheng, Hua-Hsin Yu, Wei-Jer Hsieh, Yu-Hao Hsu, Yang-Syu Lin, Che-Ju Yeh
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Publication number: 20210125662Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.Type: ApplicationFiled: June 22, 2020Publication date: April 29, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Chen Kuo, Cheng-Hung Lee, Chi-Ting Cheng, Hua-Hsin Yu, Wei-Jer Hsieh, Yu-Hao Hsu, Yang-Syu Lin, Che-Ju Yeh