Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: A memory device includes a plurality of memory cells; a word line, connected to one of the plurality of memory cells, that is configured to provide a first WL pulse having a rising edge and a falling edge that define a pulse width of the first WL pulse; a first tracking WL, formed adjacent to the memory cells, that is configured to provide, via being physically or operatively coupled to a bit line (BL) configured to write a logic state to the memory cell, a second WL pulse having a rising edge with a decreased slope; and a first tracking BL, configured to emulate the BL, that is coupled to the first tracking WL such that the pulse width of the first WL pulse is increased based on the decreased slope of the rising edge of the second WL pulse.

Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.

Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

Abstract: A power management circuit suitable for a memory device and a memory device is provided. The power management circuit includes a first logic circuit, a second logic circuit, and a transmission gate. The first logic circuit is configured to receive an inverted first input signal and a second input signal and generates a first output signal. The second logic circuit is configured to receive a first input signal and the second input signal and generates a second output signal. The transmission gate is configured to receive the first output signal and generates a control signal to at least one power transistor coupled between the power management circuit and the memory device. During a standby mode, the power transistor is turned on to make a first voltage equal to a predetermined voltage and during a sleep mode, the control signal is coupled to a first voltage. The predetermined voltage is greater than the first voltage.

Abstract: A charge sharing type lower-cell-voltage (LCV) write assist takes advantage of unused metal layers on top of a memory array to implement capacitance without incurring area costs. Only one-time fixed amount expenses of charge are needed for a given LCV level during the charge sharing phase of each write operation. Metal wires parallel to the bit cell power wires have good capacitance matching for charge sharing among all memory density configurations, thus benefitting memory compiler design.

Abstract: A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.

Abstract: A voltage selection circuit includes: a power detection circuit configured to compare an output voltage with a first input voltage and a second input voltage, respectively; a latch circuit, coupled to the power detection circuit, and configured to flip respective logic states of a pair of output signals when the output voltage is lower than either the first input voltage or the second input voltage; and a selection circuit, coupled to the latch circuit, and configured to use either the first input voltage or the second input voltage as the output voltage based on the respective logic states of the pair of output signals.

Abstract: A level shifter that comprises an input operating in an input voltage domain and an output for outputting an output signal in an output voltage domain. The level shifter further includes an inverter circuit operating in the input voltage domain for inverting an input signal to create an inverted input signal. The level shifter also includes an intermediate circuit operating in an intermediate voltage domain for generating an intermediate signal. An output buffer circuit generates the output signal based at least in part on the inverted input signal and the intermediate signal.

Abstract: A voltage selection circuit includes: a power detection circuit configured to compare an output voltage with a first input voltage and a second input voltage, respectively; a latch circuit, coupled to the power detection circuit, and configured to flip respective logic states of a pair of output signals when the output voltage is lower than either the first input voltage or the second input voltage; and a selection circuit, coupled to the latch circuit, and configured to use either the first input voltage or the second input voltage as the output voltage based on the respective logic states of the pair of output signals.

Abstract: A level shifter that comprises an input operating in an input voltage domain and an output for outputting an output signal in an output voltage domain. The level shifter further includes an inverter circuit operating in the input voltage domain for inverting an input signal to create an inverted input signal. The level shifter also includes an intermediate circuit operating in an intermediate voltage domain for generating an intermediate signal. An output buffer circuit generates the output signal based at least in part on the inverted input signal and the intermediate signal.

Abstract: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

Abstract: A memory unit that includes a tracking unit, a scan chain and a scan chain control unit. The tracking unit includes a tracking bit line, wherein the tracking unit is configured to receive a tracking control signal, selectively charge or discharge a voltage on the tracking bit line in response to the tracking control signal and generate a sense amplifier signal. The scan chain includes one or more logic devices, wherein the scan chain is configured to receive at least a first control signal. The scan chain control unit is connected to the scan chain and the tracking unit. The scan chain control unit is configured to receive the sense amplifier signal and generate the first scan chain control signal.

Abstract: An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.

Abstract: A memory unit that includes a tracking unit, a scan chain and a scan chain control unit. The tracking unit includes a tracking bit line, wherein the tracking unit is configured to receive a tracking control signal, selectively charge or discharge a voltage on the tracking bit line in response to the tracking control signal and generate a sense amplifier signal. The scan chain includes one or more logic devices, wherein the scan chain is configured to receive at least a first control signal. The scan chain control unit is connected to the scan chain and the tracking unit. The scan chain control unit is configured to receive the sense amplifier signal and generate the first scan chain control signal.

Abstract: A device includes a transistor switch coupled between a bit line voltage node and a ground node and a boost signal circuit coupled to a gate node of the transistor switch, where the boost signal circuit providing a boost signal responsive to a write enable signal. The device also includes a first delay element and a first capacitor in series with the first delay element. The first capacitor has a first end coupled to the bit line voltage node and a second end coupled to the gate node through the first delay element.

Abstract: Among other things, one or more techniques or systems for facilitating access operations to a single port memory device are provided. Multiple access operations to a single port memory device, such as a 6 transistor bitcell array of an SPSRAM, are performed during a single clock period of a system clock. In an embodiment, a wrapper controller initiates a first access operation during a first clock period of the system clock based upon a rising edge of the system clock. Responsive to receiving an operation complete signal during the first clock operation, the wrapper controller initiates a second access operation to the single port memory device during the first clock period. In this way, multi-port access functionality is implemented, such as in a serial manner to mitigate operation disturbs, for a single port memory device that occupies a relatively smaller area than a multi-port memory device for improved storage density.