Patents by Inventor Wei-Jung Lin

Wei-Jung Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200288479
    Abstract: A wireless transmit/receive unit (WTRU) may monitor control resource sets (CORESETs) to receive a physical downlink control channel (PDCCH) having downlink control information (DCI) that includes a scheduling offset and an indicated beam for a scheduled physical downlink shared channel (PDSCH) reception. When the scheduling offset of the scheduled PDSCH is less than a threshold, a default beam of a transmission configuration indication (TCI) state may be utilized to receive the scheduled PDSCH. When the scheduling offset of the scheduled PDSCH is more than a threshold, the indicated beam is utilized to receive the scheduled PDSCH on a condition that a measured quality is above a measurement threshold or the default beam may be utilized when the measured quality is below the measurement threshold.
    Type: Application
    Filed: November 15, 2018
    Publication date: September 10, 2020
    Applicant: IDAC HOLDINGS, INC.
    Inventors: Fengjun Xi, Wei Chen, Kyle Jung-Lin Pan, Moon-il Lee, Chunxuan Ye
  • Publication number: 20200247101
    Abstract: A method for preparing a bifunctional film, including: (a) drying a first polymer solution to form a film to form an anti-adhesion layer; and (b) drying a second polymer solution over the anti-adhesion layer to form a film to form an attachment layer. The first polymer solution includes a first hydrophobic solution and a first hydrophilic solution, and in the first polymer solution, the weight ratio of the solute of the first hydrophobic solution to the solute of the first hydrophilic solution 1:0.01-1. Moreover, the second polymer solution consists of a second hydrophilic solution.
    Type: Application
    Filed: November 6, 2019
    Publication date: August 6, 2020
    Applicant: Industrial Technology Research Institute
    Inventors: Hsin-Hsin SHEN, Yu-Chi WANG, Ming-Chia YANG, Yu-Bing LIOU, Wei-Hong CHANG, Yun-Han LIN, Hsin-Yi HSU, Yun-Chung TENG, Chia-Jung LU, Yi-Hsuan LEE, Jian-Wei LIN, Kun-Mao KUO, Ching-Mei CHEN
  • Publication number: 20200203222
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Application
    Filed: March 2, 2020
    Publication date: June 25, 2020
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Patent number: 10688193
    Abstract: The invention provides a pH-sensitive linker that can simultaneously bind metallic nanoparticles and one or more agents with various molecular size. The linker of the invention can deliver the agents into cells involved in disease processes or close to cells so that the agents can selectively target and effect on the cells. The target delivery provided by the linker of the invention can be used for example for disease sensing, imaging, drug delivery, and therapy.
    Type: Grant
    Filed: July 21, 2016
    Date of Patent: June 23, 2020
    Assignee: GNT BIOTECH & MEDICALS CORPORATION
    Inventors: Yu-Jung Liao, Wei-Jan Huang, Chia-Nan Chen, Huan-Yu Lin, Ching-Yi Lin, Meng-Ju Tsai, Wan-Yi Hsu, Li-Ling Chi, Ye-Su Chao, Yi-Hong Wu
  • Publication number: 20200176382
    Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.
    Type: Application
    Filed: November 13, 2019
    Publication date: June 4, 2020
    Inventors: Pin-Wen Chen, Mei-Hui Fu, Hong-Mao Lee, Wei-jung Lin, Chih-Wei Chang
  • Publication number: 20200118935
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Hong-Mao LEE, Huicheng CHANG, Chia-Han LAI, Chi-Hsuan NI, Cheng-Tung LIN, Huang-Yi HUANG, Chi-Yuan CHEN, Li-Ting WANG, Teng-Chun TSAI, Wei-Jung LIN
  • Patent number: 10619672
    Abstract: A lubricatable ball spline device includes a ball spline shaft, a ball nut slidably sleeved on the ball spline shaft and having oil guide holes, a linear bearing unit mounted between the ball spline shaft and the ball nut, a bearing ring rotatably sleeved on the ball nut and having an oil supplying hole, a positioning portion disposed between the bearing ring and the ball nut, and an oil passage corresponding to the oil supplying hole. The oil supplying hole, the oil passage, an oil storage space of the positioning portion and any one of the oil guide holes cooperatively form a continuous oil path.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: April 14, 2020
    Assignee: Hiwin Technologies Corp.
    Inventors: Wei-Chou Lin, Cheng-Ming Su, Cheng-Lung Wang, Po-Jung Huang
  • Publication number: 20200111739
    Abstract: A method for forming a semiconductor contact structure is provided. The method includes depositing a dielectric layer over a substrate. The method also includes etching the dielectric layer to expose a sidewall of the dielectric layer and a top surface of the substrate. In addition, the method includes forming a silicide region in the substrate. The method also includes applying a plasma treatment to the sidewall of the dielectric layer and the top surface of the substrate to form a nitridation region adjacent to a periphery of the silicide region. The method further includes depositing an adhesion layer on the dielectric layer and the silicide region.
    Type: Application
    Filed: December 9, 2019
    Publication date: April 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen CHENG, Wei-Yip LOH, Yu-Hsiang LIAO, Sheng-Hsuan LIN, Hong-Mao LEE, Chun-I TSAI, Ken-Yu CHANG, Wei-Jung LIN, Chih-Wei CHANG, Ming-Hsing TSAI
  • Patent number: 10580693
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: March 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20200064074
    Abstract: A condenser has a main condensing module, an auxiliary condensing module, and a connecting tube. The main condensing module has an input base tube, a first connecting base tube, and a main heat dissipating mechanism, which are series connected. The auxiliary condensing module has a second connecting base tube, an output base tube, and an auxiliary heat dissipating mechanism, which are series connected. The connecting tube is mounted between the main condensing module and the auxiliary condensing module. An interior room of the first connecting base tube communicates with an interior room of the second connecting base tube.
    Type: Application
    Filed: February 1, 2019
    Publication date: February 27, 2020
    Inventors: CHENG-CHIEN WAN, CHENG-FENG WAN, HAO-HUI LIN, TUNG-HSIN LIU, WEI-CHE HSIAO, HSIAO-CHING CHEN, DHAO-JUNG LIN
  • Patent number: 10559717
    Abstract: A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer formed on the first semiconductor layer, and an active layer formed therebetween, wherein the first semiconductor layer includes a surrounding exposed region not covered by the active layer, and the surrounding exposed region surrounds the active layer; a conductive layer formed on the second semiconductor layer, including a first conductive region extending toward and contacting the surrounding exposed region of the first semiconductor layer; an electrode layer formed on the first conductive region in the surrounding exposed region; an outside insulating layer covering a portion of the conductive layer and the electrode layer, and including a first opening exposing the other portion of the conductive layer; a bonding layer covering the outside insulating layer and electrically connecting to the other portion of the conductive layer through the first opening; and a conductive substrate, w
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: February 11, 2020
    Assignee: EPISTAR CORPORATION
    Inventors: Chun-Teng Ko, Chao-Hsing Chen, Jia-Kuen Wang, Yen-Liang Kuo, Chih-Hao Chen, Wei-Jung Chung, Chih-Ming Wang, Wei-Chih Peng, Schang-Jing Hon, Yu-Yao Lin
  • Publication number: 20200020578
    Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a barrier layer is formed along a sidewall. A portion of the barrier layer along the sidewall is etched back by a wet etching process. After etching back the portion of the barrier layer, an underlying dielectric welding layer is exposed. A conductive material is formed along the barrier layer.
    Type: Application
    Filed: July 11, 2018
    Publication date: January 16, 2020
    Inventors: Ken-Yu Chang, Chun-I Tsai, Ming-Hsing Tsai, Wei-Jung Lin
  • Publication number: 20200013674
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Patent number: 10510664
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 10504834
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Grant
    Filed: March 1, 2018
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai
  • Patent number: 10443960
    Abstract: A heat dissipating apparatus has a phase change material evaporator, a condenser, a refrigerant output tube, and a refrigerant input tube. The evaporator has a base having an evaporation chamber, a refrigerant inlet and a refrigerant outlet, a reinforcement panel mounted in the evaporation chamber and dividing the evaporation chamber into two spaces, and multiple heat conduction fins separately arranged in the two spaces. An opening area of the refrigerant outlet is larger than an opening area of the refrigerant inlet. The evaporator, the refrigerant output tube, the condenser and the refrigerant input tube form a closed refrigerant circulation loop with a refrigerant filled therein. Gas pressure of a gas-phased refrigerant in the two spaces can be increased. With pressure difference between the refrigerant outlet and the refrigerant inlet, the gas-phased refrigerant can be accelerated to flow toward the refrigerant outlet and flowability of the refrigerant can be increased.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: October 15, 2019
    Assignee: Man Zai Industrial Co., Ltd.
    Inventors: Cheng-Chien Wan, Cheng-Feng Wan, Hao-Hui Lin, Tung-Hsin Liu, Wei-Che Hsiao, Hsiao-Ching Chen, Dhao-Jung Lin
  • Patent number: 10418279
    Abstract: A semiconductor device is disclosed. The device includes a source/drain feature formed over a substrate. A dielectric layer formed over the source/drain feature. A contact trench formed through the dielectric layer to expose the source/drain feature. A titanium nitride (TiN) layer deposited in the contact trench and a cobalt layer deposited over the TiN layer in the contact trench.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: September 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Hsien Huang, Hong-Mao Lee, Hsien-Lung Yang, Yu-Kai Chen, Wei-Jung Lin
  • Publication number: 20190276595
    Abstract: A polycarbonate diol is provided, including three kinds of repeating diol units, wherein one of the repeating diol units is chosen from an alkoxylated diol monomer.
    Type: Application
    Filed: May 24, 2019
    Publication date: September 12, 2019
    Inventors: Fu-Shen Lin, June-Yen Chou, Hsing-Yun Wang, Chih-Jung Chen, Wei-Lun Hsieh
  • Patent number: 10408875
    Abstract: A testing system includes a subtractor and a divider. The subtractor is configured to receive a first voltage of a circuit being tested and a second voltage of the circuit, and to derive a difference between the first voltage and the second voltage. The divider is configured to receive the difference between the first voltage and the second voltage, and to derive a resistance of the circuit by dividing (i) the difference between the first voltage and the second voltage by (ii) a difference between a first current applied to the circuit and a second current applied to the circuit. The first voltage is corresponding to the first current, and the second voltage is corresponding to the second current.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: September 10, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Jung Chang, Wei-Kai Liao, Ming-Ching Lin, Kuei-Hao Tseng
  • Publication number: 20190273042
    Abstract: A semiconductor device and method of forming the same that includes forming a dielectric layer over a substrate and patterning a contact region in the dielectric layer, the contact region having side portions and a bottom portion that exposes the substrate. The method can also include forming a dielectric barrier layer in the contact region to cover the side portions and the bottom portion, and etching the dielectric barrier layer to expose the substrate. Subsequently, a conductive layer can be formed to cover the side portions and the bottom portion of the contact region and the conductive layer can be annealed to form a silicide region in the substrate beneath the bottom portion of the contact region, and the conductive layer can then be selectively removed on the side portions of the contact region.
    Type: Application
    Filed: March 1, 2018
    Publication date: September 5, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Wen Cheng, Wei-Yip Loh, Yu-Hsiang Liao, Sheng-Hsuan Lin, Hong-Mao Lee, Chun-I Tsai, Ken-Yu Chang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai