Patents by Inventor Wei Kang Hsieh
Wei Kang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240088050Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.Type: ApplicationFiled: November 20, 2023Publication date: March 14, 2024Inventors: Chen-Hua Yu, Wei-Kang Hsieh, Shih-Wei Chen, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 11854986Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.Type: GrantFiled: June 30, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Wei-Kang Hsieh, Shih-Wei Chen, Tin-Hao Kuo, Hao-Yi Tsai
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Publication number: 20230378098Abstract: A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hao-Yi Tsai, Tin-Hao Kuo, Shih-Wei Chen
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Patent number: 11824017Abstract: A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.Type: GrantFiled: November 6, 2022Date of Patent: November 21, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hao-Yi Tsai, Tin-Hao Kuo, Shih-Wei Chen
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Publication number: 20230223357Abstract: A method of manufacturing a semiconductor package includes depositing a first dielectric layer over a carrier substrate. A first metallization pattern is formed over the first dielectric layer. The first metallization pattern has a first opening exposing the first dielectric layer. A second dielectric layer is deposited over the first metallization pattern, forming a dielectric slot through the first metallization pattern by filling the first opening. A second metallization pattern and a third dielectric layer are formed over the second dielectric layer. A through via is formed over the third dielectric layer, so that the dielectric slot is laterally under the through via.Type: ApplicationFiled: May 24, 2022Publication date: July 13, 2023Inventors: Yi-Che Chiang, Chien-Hsun Chen, Tuan-Yu Hung, Hsin-Yu Pan, Wei-Kang Hsieh, Tsung-Hsien Chiang, Chao-Hsien Huang, Tzu-Sung Huang, Ming Hung Tseng, Wei-Chih Chen, Ban-Li Wu, Hao-Yi Tsai, Yu-Hsiang Hu, Chung-Shi Liu
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Publication number: 20230223382Abstract: A semiconductor package includes a lower semiconductor device, a plurality of conductive pillars, an upper semiconductor device, an encapsulating material, and a redistribution structure. The plurality of conductive pillars are disposed on the lower semiconductor device along a direction parallel to a side of the lower semiconductor device. The upper semiconductor device is disposed on the lower semiconductor device and reveals a portion of the lower semiconductor device where the plurality of conductive pillars are disposed, wherein the plurality of conductive pillars disposed by the same side of the upper semiconductor device and the upper semiconductor device comprises a cantilever part cantilevered over the at least one lower semiconductor device. The encapsulating material encapsulates the lower semiconductor device, the plurality of conductive pillars, and the upper semiconductor device. The redistribution structure is disposed over the upper semiconductor device and the encapsulating material.Type: ApplicationFiled: March 16, 2023Publication date: July 13, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
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Patent number: 11682626Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.Type: GrantFiled: July 10, 2020Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chen-Hua Yu, Wei-Kang Hsieh, Shih-Wei Chen, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 11646296Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.Type: GrantFiled: May 10, 2021Date of Patent: May 9, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
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Publication number: 20230066410Abstract: A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.Type: ApplicationFiled: November 6, 2022Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hao-Yi Tsai, Tin-Hao Kuo, Shih-Wei Chen
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Publication number: 20220415737Abstract: A semiconductor device includes semiconductor dies and a redistribution structure. The semiconductor dies are encapsulated in an encapsulant. The redistribution structure extends on the encapsulant and electrically connects the semiconductor dies. The redistribution structure includes dielectric layers and redistribution conductive layers alternately stacked. An outermost dielectric layer of the dielectric layers further away from the semiconductor dies is made of a first material. A first dielectric layer of the dielectric layers on which the outermost dielectric layer extends is made of a second material different from the first material. The first material includes at least one material selected from the group consisting of an epoxy resin, a phenolic resin, a polybenzooxazole, and a polyimide having a curing temperature lower than 250° C.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Chieh Wu, Ting Hao Kuo, Kuo-Lung Pan, Po-Yuan Teng, Yu-Chia Lai, Shu-Rong Chun, Mao-Yen Chang, Wei-Kang Hsieh, Pavithra Sriram, Hao-Yi Tsai, Po-Han Wang, Yu-Hsiang Hu, Hung-Jui Kuo
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Patent number: 11515268Abstract: A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.Type: GrantFiled: March 5, 2021Date of Patent: November 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hao-Yi Tsai, Tin-Hao Kuo, Shih-Wei Chen
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Publication number: 20220336361Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.Type: ApplicationFiled: June 30, 2022Publication date: October 20, 2022Inventors: Chen-Hua Yu, Wei-Kang Hsieh, Shih-Wei Chen, Tin-Hao Kuo, Hao-Yi Tsai
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Publication number: 20220285289Abstract: A semiconductor package has central region and peripheral region surrounding central region. The semiconductor package includes dies, encapsulant, and redistribution structure. The dies include functional die and first dummy dies. Functional die is disposed in central region. First dummy dies are disposed in peripheral region. Redistribution structure is disposed on encapsulant over the dies, and is electrically connected to functional die. Vacancy ratio of central region is in the range from 1.01 to 3.00. Vacancy ratio of the peripheral region is in the range from 1.01 to 3.00. Vacancy ratio of central region is a ratio of total area of central region to total area occupied by dies disposed in central region. Vacancy ratio of peripheral region is a ratio of total area of peripheral region to total area occupied by first dummy dies disposed in peripheral region.Type: ApplicationFiled: March 5, 2021Publication date: September 8, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hao-Yi Tsai, Tin-Hao Kuo, Shih-Wei Chen
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Publication number: 20210305212Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.Type: ApplicationFiled: May 10, 2021Publication date: September 30, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo-Lung Pan, Ting Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
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Publication number: 20210233852Abstract: A semiconductor device includes a die, an encapsulant over a front-side surface of the die, a redistribution structure on the encapsulant, a thermal module coupled to the back-side surface of the die, and a bolt extending through the redistribution structure and the thermal module. The die includes a chamfered corner. The bolt is adjacent to the chamfered corner.Type: ApplicationFiled: July 10, 2020Publication date: July 29, 2021Inventors: Chen-Hua Yu, Wei-Kang Hsieh, Shih-Wei Chen, Tin-Hao Kuo, Hao-Yi Tsai
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Patent number: 11004827Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.Type: GrantFiled: September 18, 2018Date of Patent: May 11, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo Lung Pan, Tin-Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun
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Publication number: 20200091114Abstract: A manufacturing method of a semiconductor package includes the following steps. At least one lower semiconductor device is provided. A plurality of conductive pillars are formed on the at least one lower semiconductor device. A dummy die is disposed on a side of the at least one lower semiconductor device. An upper semiconductor device is disposed on the at least one lower semiconductor device and the dummy die, wherein the upper semiconductor device reveals a portion of the at least one lower semiconductor device where the plurality of conductive pillars are disposed. The at least one lower semiconductor device, the dummy die, the upper semiconductor device, and the plurality of conductive pillars are encapsulated in an encapsulating material. A redistribution structure is formed over the upper semiconductor device and the plurality of conductive pillars.Type: ApplicationFiled: September 18, 2018Publication date: March 19, 2020Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Wei Kang Hsieh, Hung-Yi Kuo, Hao-Yi Tsai, Kuo Lung Pan, Tin-Hao Kuo, Yu-Chia Lai, Mao-Yen Chang, Po-Yuan Teng, Shu-Rong Chun