Abstract: A method includes forming a first select transistor of a first one-time programmable (OTP) memory bit cell over a substrate, wherein the first select transistor is of a first conductivity type; forming a first anti-fuse transistor of the first OTP memory bit cell over the substrate, wherein the first anti-fuse transistor is of a second conductivity type opposite to the first conductivity type; forming a bit line over the substrate, wherein the bit line is electrically coupled to a source/drain terminal of the first select transistor.

Abstract: A fiber array unit includes a support structure, a base on the support structure including an outer base layer, and an inner base layer attached to the outer base layer and including a recess having a recess bottom and a recess sidewall adjoining the recess bottom. The recess may be located at an interface between the outer base layer and the inner base layer and the interface may be substantially perpendicular to the support structure. The fiber array unit also includes a mirror including a reflective layer on the recess bottom and recess sidewall.

Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor triggered silicon control rectifier (SCR) and methods of manufacture. The structure includes: a vertical silicon controlled rectifier; and a triggering device adjacent to the vertical silicon controlled rectifier, the triggering device and the vertical silicon controlled rectifier sharing a diffusion region within a semiconductor substrate.

Abstract: A heating, ventilation, air conditioning, and refrigeration (HVACR) system includes an array of packaged units; and a controller to obtain an operating condition of the array of packaged units, derive the operating condition to construct an operating pattern, select one or more packaged units to be adjusted to increase efficiency of the array of packaged units based on the operating pattern, and to adjust operation of the one or more packaged units selected by the controller.

Abstract: In a method of forming a groove pattern extending in a first axis in an underlying layer over a semiconductor substrate, a first opening is formed in the underlying layer, and the first opening is extended in the first axis by directional etching to form the groove pattern.

Abstract: A method of making a semiconductor device, includes: forming a first molding layer on a substrate; forming a first plurality of vias in the first molding layer; forming a first conductive line over the first molding layer, wherein the first conductive line is laterally disposed over the first molding layer and a first end of the conductive line aligns with and is electrically coupled to a first via of the first plurality of vias; forming a second molding layer above the first molding layer; and forming a second plurality of vias in the second molding layer, wherein a second via of the second plurality of vias aligns with and is electrically coupled to a second end of the conductive line, and wherein the second plurality of vias, the conductive line, and the first plurality of vias are electrically coupled to one another.

Abstract: A current transformer is provided, including a ferrite core and a coil. The ferrite core is formed in an open shape, having a first contact surface and a second contact surface. The coil is wound around the ferrite core, wherein when an induced current signal is generated in the coil, an imaginary line of the magnetic field extends through either the first contact surface or the second contact surface.

Abstract: The present application relates to the technical field of computers. A security authentication method, apparatus and system for a digital currency transaction. A specific embodiment of the method includes: a first terminal device storing a first certificate issued by a digital currency issuing end and second certificates issued by one or more digital currency operation ends; the first terminal device receiving a third certificate sent by a first digital currency operation end, and performing signature verification on the third certificate by using a second certificate, which is issued by the first digital currency operation end and passes signature verification; and after the third certificate passes the signature verification, the first terminal device performing a digital currency transaction with the first digital currency operation end and/or a second terminal device, wherein the second terminal device stores a fourth certificate sent by a second digital currency operation end.

Abstract: A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.

Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.

Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.

Abstract: A method is described herein of making a textured glass article, the method includes: etching an initial primary surface of a glass substrate having a thickness with a hydrofluoric acid-free etchant having a pH of about 3 or less; and removing the etchant from the glass substrate, such that the etching is conducted from above ambient temperature to about 100° C. to form a textured region that is defined by a primary surface of the substrate and comprises a sparkle of 2% or less, and the etching comprises a plurality of batch cycles.

Abstract: A humidifier comprises a water reservoir and a reservoir dock configured to receive the water reservoir in an operative position. The water reservoir is configured to hold a volume of liquid. The water reservoir includes a chamber and a single conduit providing an inner opening arranged within the chamber. The reservoir dock includes a dock inlet conduit arranged to receive the flow of air from the RPT device. The dock inlet conduit is structured and arranged to extend within the single conduit of the water reservoir when the water reservoir reaches the operative position such that the dock inlet conduit and the single conduit at least partially overlap one another.

Abstract: A chip package structure is provided. The chip package structure includes a photonic integrated circuit chip including a dielectric structure, a photodetector, an optical modulator, and a first waveguide structure in the dielectric structure. The photodetector and the optical modulator are connected to the first waveguide structure. The chip package structure includes an electronic integrated circuit chip over the photonic integrated circuit chip. The chip package structure includes an optical transmission chip over the photonic integrated circuit chip. The optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure.

Abstract: The disclosure provides an electronic device including a substrate, a first vibrating unit, and a supporting unit. The substrate has a first surface. The first vibrating unit is disposed on the first surface and has a second surface. The second surface faces the first surface. The supporting unit is disposed between the substrate and the first vibrating unit. The first surface and the second surface are separated by a distance through the supporting unit. This distance ranges from equal to or greater than 0.06 mm to equal to or less than 65.4 mm.

Abstract: A polymer composite for preparing a low dielectric resin composition having a dielectric loss tangent (Df) that is less than or equal to 0.00200 is provided. The polymer composite includes a first styrene-based copolymer having a weight average molecular weight that is lower than 20,000 g/mol and a second styrene-based copolymer having a weight average molecular weight that is higher than 20,000 g/mol, wherein the weight ratio of the first styrene-based copolymer to the second styrene-based copolymer is from 5/95 to 95/5.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to silicon controlled rectifiers and methods of manufacture. The structure includes: a plurality of wells of a first conductivity type; a well of a second conductivity type which is different than the first conductivity type; an intrinsic semiconductor region between the well and the plurality of wells; and contacts within the plurality of wells.