Patents by Inventor Wei Liang

Wei Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250150828
    Abstract: A method, apparatus, and computer-readable medium for improving the reliability of a wireless communication network. The reliability of the wireless communication network is improved by: determining an integrity protection key of a ranging announcement message according to long-term key information sent from a core network, where the integrity protection key is configured to replace a discovery key for integrity protection of the ranging announcement message in a case where the first UE is unable to obtain the discovery key from a mobile communication network.
    Type: Application
    Filed: January 29, 2022
    Publication date: May 8, 2025
    Applicant: Beijing Xiaomi Mobile Software Co., Ltd.
    Inventors: Haoran LIANG, Wei LU
  • Publication number: 20250149004
    Abstract: A display device and an operating method for the display device are provided. The display device includes a pixel array, a multiplexer circuit, and a holding circuit. The pixel array includes a first pixel column and a second pixel column. The multiplexer circuit provides a first data signal to the first pixel column during a first period and provides a second data signal to the second pixel column during a second period. The holding circuit provides a reference signal to the second pixel column during the first period to maintain a display result of the second pixel column during a previous period and provides the reference signal to the first pixel column during the second period to maintain a display result of the first pixel column during the first period.
    Type: Application
    Filed: August 28, 2024
    Publication date: May 8, 2025
    Applicant: E Ink Holdings Inc.
    Inventors: Chi-Liang Wu, Wei-Tsung Chen
  • Publication number: 20250149438
    Abstract: A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.
    Type: Application
    Filed: January 7, 2025
    Publication date: May 8, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Wei-Ren WANG, Tze-Liang LEE, Jen-Hung WANG
  • Publication number: 20250149488
    Abstract: In an embodiment, a method includes forming a device region along a first substrate; forming an interconnect structure over the device region and the first substrate; forming a metal pillar over the interconnect structure, forming the metal pillar comprising: forming a base layer over the interconnect structure; forming an intermediate layer over the base layer; and forming a capping layer over the intermediate layer; forming a solder region over the capping layer; and performing an etch process to recess sidewalls of the base layer and the capping layer from sidewalls of the intermediate layer and the solder region.
    Type: Application
    Filed: February 23, 2024
    Publication date: May 8, 2025
    Inventors: Wei-Yu Chen, Chao-Wei Chiu, Hsin Liang Chen, Hao-Jan Shih, Hao-Jan Pei, Hsiu-Jen Lin
  • Publication number: 20250149343
    Abstract: In a method of manufacturing a semiconductor device, an underlying structure is formed over a substrate. A film is formed over the underlying structure. Surface topography of the film is measured and the surface topography is stored as topography data. A local etching is performed by using directional etching and scanning the substrate so that an entire surface of the film is subjected to the directional etching. A plasma beam intensity of the directional etching is adjusted according to the topography data.
    Type: Application
    Filed: January 10, 2025
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Wen YEH, Yu-Tien SHEN, Shih-Chun HUANG, Po-Chin CHANG, Wei-Liang LIN, Yung-Sung YEN, Wei-Hao WU, Li-Te LIN, Pinyen LIN, Ru-Gun LIU
  • Publication number: 20250144640
    Abstract: Provided are a high-pressure jet impact chamber structure, with an industrial-grade “single orifice+single pulverizing chamber” design, and a multi-parallel type convenient pulverizing component adopted with the high-pressure jet impact chamber structure. The high-pressure jet impact chamber structure includes a body, a jet orifice, and a pulverizing chamber. The multi-parallel type convenient pulverizing component adopted with the high-pressure jet impact chamber structure includes a multi-parallel type chassis, a multi-parallel type connector disk, multiple high-pressure jet impact chamber structures that are parallel to each other, a sealing end cover, a discharge disk, and a discharge pipe.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 8, 2025
    Inventors: JUN CHEN, JIALONG HAN, TAOTAO DAI, LIZHEN DENG, CHENGMEI LIU, RUIHONG LIANG, WEI LIU
  • Publication number: 20250151368
    Abstract: A semiconductor device and methods of fabricating the same are disclosed. The semiconductor device includes a substrate, a fin structure with a fin top surface disposed on the substrate, a source/drain (S/D) region disposed on the fin structure, a gate structure disposed on the fin top surface, and a gate spacer with first and second spacer portions disposed between the gate structure and the S/D region. The first spacer portion extends above the fin top surface and is disposed along a sidewall of the gate structure. The second spacer portion extends below the fin top surface and is disposed along a sidewall of the S/D region.
    Type: Application
    Filed: January 6, 2025
    Publication date: May 8, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Liang LU, Chang-Yin CHEN, Chih-Han LIN, Chia-Yang LIAO
  • Patent number: 12290638
    Abstract: A humidifier comprises a water reservoir and a reservoir dock configured to receive the water reservoir in an operative position. The water reservoir is configured to hold a volume of liquid. The water reservoir includes a chamber and a single conduit providing an inner opening arranged within the chamber. The reservoir dock includes a dock inlet conduit arranged to receive the flow of air from the RPT device. The dock inlet conduit is structured and arranged to extend within the single conduit of the water reservoir when the water reservoir reaches the operative position such that the dock inlet conduit and the single conduit at least partially overlap one another.
    Type: Grant
    Filed: June 24, 2021
    Date of Patent: May 6, 2025
    Assignee: ResMed Pty Ltd
    Inventors: Joseph Samuel Ormrod, Michael James Dent, Wei Liang Lau
  • Patent number: 12294121
    Abstract: An end cover assembly includes: an end cover with a through hole for injecting electrolyte and a first clamping portion, wherein the first clamping portion is disposed along a circumferential direction of the through hole and is located on one side of the end cover away from an interior of the battery cell; a sealing ring for sealing the through hole; and a pressure relief device covering at least part of the sealing ring and closing the through hole; wherein the pressure relief device includes a second clamping portion, and is rotatable such that when the pressure relief device is rotated to a first position, the second clamping portion is clamped with the first clamping portion; and when the pressure relief device is rotated to a second position, the second clamping portion is disengaged from the first clamping portion.
    Type: Grant
    Filed: September 7, 2020
    Date of Patent: May 6, 2025
    Assignee: Contemporary Amperex Technology (Hong Kong) Limited
    Inventors: Xinxiang Chen, Shoujun Huang, Yulian Zheng, Peng Wang, Wei Li, Chengdu Liang
  • Patent number: 12293278
    Abstract: A semantic segmentation network model uncertainty quantification method based on evidence inference. The method comprises the steps of constructing an FCN network model, and training the FCN network model by using a training data set to obtain a trained FCN network model for semantic segmentation of image data; transplanting a D-S theory of evidence to the trained FCN network model to obtain a reconstructed FCN network model; and inputting to-be-segmented image data into the reconstructed FCN network model, outputting a classification result of a to-be-segmented image by the FCN network model, and calculating a classification result uncertainty value of each pixel point by using the D-S theory of evidence index.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: May 6, 2025
    Assignee: Beijing Jiaotong University
    Inventors: Rui Wang, Ci Liang, Wei Zheng, Yumei Zhang
  • Patent number: 12293919
    Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer (e.g., spacer footing) needs to be selectively etched in a presence of an exposed silicon-containing layer, such as SiOC, SiON, SiONC, amorphous silicon, SiC, or SiN. In order to reduce damage to the silicon-containing layer the process involves passivating the silicon-containing layer towards a tin oxide etch chemistry, etching the tin oxide, and repeating passivation and etch in an alternating fashion. For example, passivation and etch can be each performed between 2-50 times. In one implementation, passivation is performed by treating the substrate with an oxygen-containing reactant, activated in a plasma, and the tin oxide etching is performed by a chlorine-based chemistry, such as using a mixture of Cl2 and BCl3.
    Type: Grant
    Filed: November 8, 2023
    Date of Patent: May 6, 2025
    Assignee: Lam Research Corporation
    Inventors: Seongjun Heo, Jengyi Yu, Chen-Wei Liang, Alan J. Jensen, Samantha S. H. Tan
  • Patent number: 12291479
    Abstract: A method is described herein of making a textured glass article, the method includes: etching an initial primary surface of a glass substrate having a thickness with a hydrofluoric acid-free etchant having a pH of about 3 or less; and removing the etchant from the glass substrate, such that the etching is conducted from above ambient temperature to about 100° C. to form a textured region that is defined by a primary surface of the substrate and comprises a sparkle of 2% or less, and the etching comprises a plurality of batch cycles.
    Type: Grant
    Filed: August 6, 2020
    Date of Patent: May 6, 2025
    Assignee: CORNING INCORPORATED
    Inventors: Li-Wei Chou, Jiangwei Feng, Jhih-Wei Liang
  • Publication number: 20250138345
    Abstract: An electro-optical device includes a waveguide and a first electrode and a second electrode. The first electrode and the second electrode at first and second sides of the waveguide, wherein the first electrode and the second electrode directly contact and extend beyond the first and second sides of the waveguide respectively.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuen-Shin Liang, Tsung-Fu Tsai, Szu-Wei Lu, Chung-Shi Liu, Chen-Hua Yu
  • Publication number: 20250138258
    Abstract: A chip package structure is provided. The chip package structure includes a photonic integrated circuit chip including a dielectric structure, a photodetector, an optical modulator, and a first waveguide structure in the dielectric structure. The photodetector and the optical modulator are connected to the first waveguide structure. The chip package structure includes an electronic integrated circuit chip over the photonic integrated circuit chip. The chip package structure includes an optical transmission chip over the photonic integrated circuit chip. The optical transmission chip includes a substrate, a second waveguide structure, and a first reflective structure.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih-Wei LIANG, Jiun-Yi WU
  • Publication number: 20250138283
    Abstract: A coupled lens structure for a mixed/augmented reality system includes: a lens tube; a first lens with a first aspherical light input surface coupled to a lens-tube light input surface; a second lens with a second spherical light input surface optically coupled to a first spherical light output surface of the first lens; a third lens with a third spherical light input surface optically coupled to a second aspherical light output surface of the second lens; and a fourth lens with a fourth spherical light input surface optically coupled to a third spherical light output surface of the third lens and a fourth spherical light output surface coupled to a lens-tube light output surface. The coupled lens structure has volume of 2.1-3 cc, a lens-tube outer diameter of 12-13.5 mm, and a full angle of view not greater than 30 degrees, featuring an effective reduction in volume and weight.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 1, 2025
    Inventors: Ying-Shun SHIU, Guan-Wei HUANG, Jun-Yi YU, Wen-Hsin SUN, Wei-Chia SU, Wen-Kai LIN, Shao-Kui ZHOU, Yuan-Yan LIANG, Ching-Cherng SUN
  • Patent number: 12288373
    Abstract: The present disclosure provides a method of processing an image, an electronic device, and a storage medium, which may be used in a field of artificial intelligence, especially in a field of image processing, etc. The method includes: acquiring an input image containing a plurality of rows of pixels; performing, by using a plurality of dedicated processing units, a pixel extraction in parallel on each row of pixels of the plurality of rows of pixels in the input image, so as to obtain row data for each row of pixels; and stitching the row data for each row of pixels, so as to obtain an output image.
    Type: Grant
    Filed: August 8, 2022
    Date of Patent: April 29, 2025
    Assignee: KUNLUNXIN TECHNOLOGY (BEIJING) COMPANY LIMITED
    Inventors: Zihao Liang, Jian Ouyang, Wei Qi, Jing Wang
  • Patent number: 12288723
    Abstract: A method includes forming first and second gate stacks extending across a semiconductor fin on a substrate; forming source/drain regions in the semiconductor fin, wherein one of the source/drain region is between the first and second gate stacks; forming a dielectric layer laterally surrounding the first and second gate stacks; doping a portion of the dielectric layer between the first and second gate stacks with a dopant; removing the second gate stack to form a gate trench next to the doped first portion of the dielectric layer; performing an annealing process to expand the doped first portion of the dielectric layer toward the gate trench; forming an isolation structure in the gate trench and next to the expanded first portion of the dielectric layer; forming a source/drain contact extending through the dielectric layer to the one of the source/drain regions.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: April 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wei Wu, Hsin-Che Chiang, Chun-Sheng Liang
  • Patent number: 12288918
    Abstract: There is provided a phase shifter having a phase shift region and a peripheral region, and including a first substrate, a second substrate and a dielectric layer between such two substrates; the first substrate includes a first dielectric substrate, a first electrode and a first auxiliary structure; the second substrate includes a second dielectric substrate, a second electrode and a second auxiliary structure; the phase shift region includes overlapping regions; the first electrode and the second electrode are located in the phase shift region, and have orthographic projections, on the first dielectric substrate, overlapped at least partially in the overlapping regions; the first auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the first dielectric substrate; the second auxiliary structure is in the peripheral region and on a side, close to the dielectric layer, of the second dielectric substrate.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: April 29, 2025
    Assignees: Beijing BOE Sensor Technology Co., Ltd., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiaobo Wang, Haocheng Jia, Chuncheng Che, Zhifeng Zhang, Cuiwei Tang, Yong Liu, Honggang Liang, Sheng Chen, Xueyan Su, Hailong Lian, Yi Ding, Jing Xie, Wei Zhang, Weisi Zhou, Meng Wei, Jing Wang, Zhenguo Zhang, Feng Qu
  • Patent number: 12289580
    Abstract: The disclosure provides an electronic device including a substrate, a first vibrating unit, and a supporting unit. The substrate has a first surface. The first vibrating unit is disposed on the first surface and has a second surface. The second surface faces the first surface. The supporting unit is disposed between the substrate and the first vibrating unit. The first surface and the second surface are separated by a distance through the supporting unit. This distance ranges from equal to or greater than 0.06 mm to equal to or less than 65.4 mm.
    Type: Grant
    Filed: December 20, 2022
    Date of Patent: April 29, 2025
    Assignee: Innolux Corporation
    Inventors: Jui-Jen Yueh, Kuan-Feng Lee, Tsung-Han Tsai, Shun-Cheng Chen, Ting-Wei Liang
  • Publication number: 20250130189
    Abstract: Disclosed herein is an electrochemical characterization apparatus and system that facilitates high-throughput measurements of various different properties and/or performance characteristics of components of an energy storage and conversion device, such as an electrolyte and/or electrodes. Also disclosed are methods for using the electrochemical characterization apparatus and system.
    Type: Application
    Filed: October 20, 2023
    Publication date: April 24, 2025
    Inventors: Yangang Liang, Wei Wang, Heather M. Job, Juran Noh, Jie Bao, Will Dean, Ruozhu Feng, Jing Wu