Patents by Inventor Wei Liang
Wei Liang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145581Abstract: In a method of manufacturing a semiconductor device, a fin structure having a channel region protruding from an isolation insulating layer disposed over a semiconductor substrate is formed, a cleaning operation is performed, and an epitaxial semiconductor layer is formed over the channel region. The cleaning operation and the forming the epitaxial semiconductor layer are performed in a same chamber without breaking vacuum.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Wen CHIU, Yi Che CHAN, Lun-Kuang TAN, Zheng-Yang PAN, Cheng-Po CHAU, Pin-Chu LIANG, Hung-Yao CHEN, De-Wei YU, Yi-Cheng LI
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Patent number: 11972956Abstract: A lid attach process includes dipping a periphery of a lid in a dipping tank of adhesive material such that the adhesive material attaches to the periphery of the lid. The lid attach process further includes positioning the lid over a die attached to a substrate using a lid carrier, wherein the periphery of the lid is aligned with a periphery of the lid carrier. The lid attach process further includes attaching the lid to the substrate with the adhesive material forming an interface with the substrate. The lid attach process further includes contacting a thermal interface material (TIM) on the die with the lid.Type: GrantFiled: May 22, 2020Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chin-Liang Chen, Wei-Ting Lin, Yu-Chih Liu, Kuan-Lin Ho, Jason Shen
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Patent number: 11971555Abstract: An optical system including an enclosure including a front end and a rear end, a first pair of apertures configured to be disposed on a front plane on the front end of the enclosure and a single optical lens system disposed between the front end and the rear end of the enclosure, wherein the first pair of apertures are configured to allow sets of light rays into the enclosure through the single optical lens system to be cast on an image plane as first and second spots, the image plane being parallel to the front plane, if the first and second spots are concentrically disposed, the sets of light rays are determined to be parallelly disposed with respect to one another, otherwise the sets of light rays are determined to not be parallelly disposed with one another.Type: GrantFiled: October 30, 2023Date of Patent: April 30, 2024Assignee: MLOptic Corp.Inventors: Pengfei Wu, Siyuan Liang, Wei Zhou
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Patent number: 11974371Abstract: A light-emitting diode LED driver and a LED driving device including the LED driver are provided. The light-emitting diode LED driver includes a decoding circuit that receives a data signal and decodes the data signal to generate display data used to drive LEDs to emit light and display and a recovered clock signal. Further provided is an encoding circuit that encodes the decoded display data by using the recovered clock signal to generate an encoded data signal, where the data signal is encoded in a first encoding format, and the encoded data signal is encoded in a second encoding format.Type: GrantFiled: July 29, 2021Date of Patent: April 30, 2024Assignee: NOVATEK MICROELECTRONICS CORP.Inventors: Yu-Hsiang Wang, Che-Wei Yeh, Keko-Chun Liang, Yong-Ren Fang, Yi-Chuan Liu
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Patent number: 11973148Abstract: A semiconductor device and a method of forming the same is disclosed. The semiconductor device includes a substrate, a first well region disposed within the substrate, a second well region disposed adjacent to the first well region and within the substrate, and an array of well regions disposed within the first well region. The first well region includes a first type of dopants, the second well region includes a second type of dopants that is different from the first type of dopants, and the array of well regions include the second type of dopants. The semiconductor device further includes a metal silicide layer disposed on the array of well regions and within the substrate, a metal silicide nitride layer disposed on the metal silicide layer and within the substrate, and a contact structure disposed on the metal silicide nitride layer.Type: GrantFiled: November 18, 2021Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ting-Ying Wu, Yung-Hsiang Chen, Yu-Lung Yeh, Yen-Hsiu Chen, Wei-Liang Chen, Ying-Tsang Ho
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Patent number: 11972974Abstract: An IC structure includes a transistor, a source/drain contact, a metal oxide layer, a non-metal oxide layer, a barrier structure, and a via. The transistor includes a gate structure and source/drain regions on opposite sides of the gate structure. The source/drain contact is over one of the source/drain regions. The metal oxide layer is over the source/drain contact. The non-metal oxide layer is over the metal oxide layer. The barrier structure is over the source/drain contact. The barrier structure forms a first interface with the metal oxide layer and a second interface with the non-metal oxide layer, and the second interface is laterally offset from the first interface. The via extends through the non-metal oxide layer to the barrier structure.Type: GrantFiled: January 13, 2022Date of Patent: April 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Sung-Li Wang, Shuen-Shin Liang, Yu-Yun Peng, Fang-Wei Lee, Chia-Hung Chu, Mrunal Abhijith Khaderbad, Keng-Chu Lin
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Patent number: 11971038Abstract: A single-stage enthalpy enhancing rotary compressor and an air conditioner having same. The single-stage enthalpy enhancing rotary compressor includes: at least one single-stage cylinder, a rotator, an upper flange, and a lower flange. The rotator is arranged inside the cylinder and is rotatable, a compression chamber is formed between the rotator and an inner peripheral wall of the cylinder, a vapor injection opening is defined in at least one of the upper flange the lower flange, and the vapor injection opening is configured to supply gas outside the compressor to the compression chamber directly. According to the present disclosure, two-stage compression is realized without adding an extra cylinder, thereby effectively enhancing a circulation of refrigerant, improving cooling performance of the air conditioner under high environmental temperatures.Type: GrantFiled: September 26, 2022Date of Patent: April 30, 2024Assignee: GREE ELECTRIC APPLIANCES, INC. OF ZHUHAIInventors: Guanghui Xia, Xiaocheng Lai, Shuo Xiong, Junchu Liang, Boming Zhu, Lihui Zhang, Wei Zhu, Xuechao Ding, Fuqiang Zhang, Hao Mei
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Patent number: 11970945Abstract: A hole protection system and a method for coal seam slotting and fracturing combined drainage. The system includes a hydraulic slotting subsystem, a hydraulic fracturing subsystem and a flexible hole protection system. The hydraulic slotting subsystem includes an ultra-high pressure water jet generating module, a drill pipe drilling tool module, an orifice sealer, a gas slag separator and a drilling rig. The hydraulic fracturing system includes an emulsion pump station, a water tank, a hole sealing device, a fracturing string and a casing. The flexible hole protection system includes a front end fixing device, a water injection support pipe, a first flexible support and a water injection connecting section.Type: GrantFiled: March 17, 2023Date of Patent: April 30, 2024Assignees: Hancheng Zaozhuang Industrial Co., Ltd., Chongqing UniversityInventors: Xiaoyan Sun, Quanle Zou, Qican Ran, Peimiao Sang, Jinyan Liang, Ning Li, Wei Pi
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Publication number: 20240131988Abstract: The present invention is related to a rear view mirror steering structure.Type: ApplicationFiled: September 10, 2023Publication date: April 25, 2024Inventor: Chung-Wei Liang
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Publication number: 20240128147Abstract: A semiconductor device is provided. The semiconductor includes a supporting silicon layer and a memory module. The memory module and the supporting silicon layer are bonded via a bonding structure. The bonding structure includes at least one bonding film whose thickness is less than 200 ?.Type: ApplicationFiled: January 20, 2023Publication date: April 18, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sey-Ping SUN, Chen-Hua YU, Shih Wei LIANG
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Publication number: 20240124437Abstract: The present disclosure relates to an injectable lurasidone suspension and a preparation method thereof, and in particular to an irregular form of a lurasidone solid and a pharmaceutical composition thereof. The present disclosure also relates to a preparation method for the solid and the pharmaceutical composition thereof, and an application thereof in the treatment of mental diseases. According to the present disclosure, the lurasidone solid prepared has controllable particle size and has Dv5O particle size of 6 ?m to 110 ?m. The good particle size stability can also he maintained in the pharmaceutical composition. The lurasidone suspension preparation obtained by the method is fast-acting, has a long sustained release period, and can effectively reduce the risk caused by poor patient compliance.Type: ApplicationFiled: March 21, 2022Publication date: April 18, 2024Inventors: Ming LI, Xiangyong LIANG, Zhengxing SU, Dan LI, Duo KE, Cong YI, Wei WEI, Guifu DENG, Ya PENG, Dong ZHAO, Jingyi WANG
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Publication number: 20240120388Abstract: Provided are structures and methods for forming structures with sloping surfaces of a desired profile. An exemplary method includes performing a first etch process to differentially etch a gate material to a recessed surface, wherein the recessed surface includes a first horn at a first edge, a second horn at a second edge, and a valley located between the first horn and the second horn; depositing an etch-retarding layer over the recessed surface, wherein the etch-retarding layer has a central region over the valley and has edge regions over the horns, and wherein the central region of the etch-retarding layer is thicker than the edge regions of the etch-retarding layer; and performing a second etch process to recess the horns to establish the gate material with a desired profile.Type: ApplicationFiled: January 18, 2023Publication date: April 11, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Li-Wei Yin, Tzu-Wen Pan, Yu-Hsien Lin, Jih-Sheng Yang, Shih-Chieh Chao, Chia Ming Liang, Yih-Ann Lin, Ryan Chia-Jen Chen
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Publication number: 20240120239Abstract: A method for modulating a threshold voltage of a device. The method includes providing a fin extending from a substrate, where the fin includes a plurality of semiconductor channel layers defining a channel region for a P-type transistor. In some embodiments, the method further includes forming a first gate dielectric layer surrounding at least three sides of each of the plurality of semiconductor channel layers of the P-type transistor. Thereafter, the method further includes forming a P-type metal film surrounding the first gate dielectric layer. In an example, and after forming the P-type metal film, the method further includes annealing the semiconductor device. After the annealing, and in some embodiments, the method includes removing the P-type metal film.Type: ApplicationFiled: March 10, 2023Publication date: April 11, 2024Inventors: Cheng-Wei CHANG, Chi-Yu CHOU, Lun-Kuang TAN, Shuen-Shin LIANG
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Publication number: 20240120018Abstract: A memory device, a failure bits detector, and a failure bits detection method thereof are provided. The failure bits detector includes a current generator, a current mirror, and a comparator. The current generator generates a first current according to a reference code. The current mirror mirrors the first current to generate a second current at a second end of the current mirror. The comparator compares a first voltage at a first input end with a second voltage at a second input end to generate a detection result.Type: ApplicationFiled: October 5, 2022Publication date: April 11, 2024Applicant: MACRONIX International Co., Ltd.Inventors: Chung-Han Wu, Che-Wei Liang, Chih-He Chiang, Shang-Chi Yang
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Patent number: 11955338Abstract: A method includes providing a substrate having a surface such that a first hard mask layer is formed over the surface and a second hard mask layer is formed over the first hard mask layer, forming a first pattern in the second hard mask layer, where the first pattern includes a first mandrel oriented lengthwise in a first direction and a second mandrel oriented lengthwise in a second direction different from the first direction, and where the first mandrel has a top surface, a first sidewall, and a second sidewall opposite to the first sidewall, and depositing a material towards the first mandrel and the second mandrel such that a layer of the material is formed on the top surface and the first sidewall but not the second sidewall of the first mandrel.Type: GrantFiled: January 30, 2023Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shih-Chun Huang, Ya-Wen Yeh, Chien-Wen Lai, Wei-Liang Lin, Ya Hui Chang, Yung-Sung Yen, Ru-Gun Liu, Chin-Hsiang Lin, Yu-Tien Shen
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Patent number: 11954442Abstract: The present disclosure is directed to systems and methods for performing reading comprehension with machine learning. More specifically, the present disclosure is directed to a Neural Symbolic Reader (example implementations of which may be referred to as NeRd), which includes a reader to encode the passage and question, and a programmer to generate a program for multi-step reasoning. By using operators like span selection, the program can be executed over a natural language text passage to generate an answer to a natural language text question. NeRd is domain-agnostic such that the same neural architecture works for different domains. Further, NeRd is compositional such that complex programs can be generated by compositionally applying the symbolic operators.Type: GrantFiled: August 6, 2020Date of Patent: April 9, 2024Assignee: GOOGLE LLCInventors: Chen Liang, Wei Yu, Quoc V. Le, Xinyun Chen, Dengyong Zhou
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Patent number: 11955472Abstract: Disclosed are embodiments of a semiconductor structure that includes a semiconductor-controlled rectifier (e.g., for electrostatic discharge (ESD) protection). The SCR can be readily integrated into advanced semiconductor-on-insulator processing technology platforms (e.g., a fully depleted silicon-on-insulator (FDSOI) processing technology platform) that employ hybrid semiconductor substrates (i.e., semiconductor substrates with both bulk semiconductor and semiconductor-on-insulator regions) and is configured with an on-Pwell semiconductor-on-insulator gate structure that is tied to an anode terminal to effectively lower the SCR trigger voltage. To further lower the trigger voltage of the SCR, the Pwell on which the gate structure sits may be made narrower than the gate structure and/or the doping profile of the Pwell on which the gate structure sits may be graded (e.g., P to P? closer to insulator layer).Type: GrantFiled: December 17, 2021Date of Patent: April 9, 2024Assignee: GlobalFoundries U.S. Inc.Inventors: Meng Miao, Alain Loiseau, Souvick Mitra, Wei Liang, Robert J. Gauthier, Jr., Anindya Nath
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Patent number: 11956372Abstract: The present invention relates to a judgment method for edge node computing result trustworthiness based on trust evaluation, and belongs to the technical field of data processing. By means of the present invention, a security mechanism for trustworthiness of a computing result output by an industrial edge node is guaranteed, the industrial edge node is prevented from outputting error data, and attacks of false data of malicious edge nodes are resisted, it is guaranteed that trustworthy computing results not be tampered are input in the industrial cloud, and a site device is made to receive correct computing results rather than malicious or meaningless messages, thereby improving efficiency and security of industrial production.Type: GrantFiled: July 15, 2020Date of Patent: April 9, 2024Assignee: CHONGQING UNIVERSITY OF POSTS AND TELECOMMUNICATIONSInventors: Min Wei, Er Xiong Liang, Ping Wang
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Publication number: 20240111597Abstract: A present invention embodiment requests resources for a set of tasks from different resource providers. The set of tasks includes first tasks and second tasks of longer duration than the first tasks. The resources are revocable by the different resource providers based on processing demand. Performance of the first tasks is initiated on the resources, and stable resources are identified based on revocation of the resources during performance of the first tasks. Performance of the second tasks are initiated on the identified stable resources. Requests for the resources to the different resource providers are adjusted based on resource provider information collected in response to completion of the set of tasks.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Guang Han Sui, Wei Ge, Lan Zhe Liu, Guo Liang Wang
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Patent number: D1023135Type: GrantFiled: April 25, 2023Date of Patent: April 16, 2024Assignee: Novium Taiwan Inc.Inventors: Kuo-Hung Liang, Ming-Wei Kuo