Abstract: The present disclosure describes an apparatus with a local interconnect structure. The apparatus can include a first transistor, a second transistor, a first interconnect structure, a second interconnect structure, and a third interconnect structure. The local interconnect structure can be coupled to gate terminals of the first and second transistors and routed at a same interconnect level as reference metal lines coupled to ground and a power supply voltage. The first interconnect structure can be coupled to a source/drain terminal of the first transistor and routed above the local interconnect structure. The second interconnect structure can be coupled to a source/drain terminal of the second transistor and routed above the local interconnect structure. The third interconnect structure can be routed above the local interconnect structure and at a same interconnect level as the first and second interconnect structures.

Abstract: A digital currency payment method and system, and an apparatus, a security chip, and an application method, which relate to the technical field of computers. The payment method includes: generating a transaction amount, or acquiring, by means of a communication connection between a first client and a second client, the transaction amount sent by the second client; and sending a payment request to the second client by means of the communication connection, where the payment request indicates a first digital currency corresponding to the transaction amount or a circulation identifier of the first digital currency, so as to enable a second currency management apparatus corresponding to the second client to cash a second digital currency corresponding to the transaction amount to a first currency management apparatus corresponding to the first client.

Abstract: A memory device and a method for operating the same are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.

Abstract: A digital currency payment method and system, and an apparatus, a security chip, and an application method, which relate to the technical field of computers. The payment method includes: generating a transaction amount, or acquiring, by means of a communication connection between a first client and a second client, the transaction amount sent by the second client; and sending a payment request to the second client by means of the communication connection, where the payment request indicates a first digital currency corresponding to the transaction amount or a circulation identifier of the first digital currency, so as to enable a second currency management apparatus corresponding to the second client to cash a second digital currency corresponding to the transaction amount to a first currency management apparatus corresponding to the first client.

Abstract: A computing system generates directives of a program. Beam nodes are selected one level at a time from multiple nodes in the tree structure. Each node represents a subset of operations in the program. A first number of the beam nodes are selected at a given level of the tree structure. The selection of the first number of the beam nodes uses a cost model that is based on a neural network. A second number of the beam nodes are selected using a random search. The ratio of the first number to the second number is determined based on a search completion percentage at the given level. A path is identified that passes through respective beam nodes at multiple levels of the tree structure. The path represents a schedule for executing the program on a target machine. Then the directives corresponding to the schedule are generated.

Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

Abstract: A method of reducing corner rounding during patterning of a substrate to form a prescribed pattern comprising a corner includes dividing the pattern into a first pattern and a second pattern, the first pattern forming a first edge of the corner and the second pattern forming a second edge of the corner. At least a portion of the second pattern overlaps the first pattern such that the first edge intersects with the second edge to form a corner of the prescribed pattern. The method further includes forming the first pattern in a first mask layer disposed on a substrate to expose the substrate and forming the second pattern in the first mask layer to expose the substrate. The substrate exposed through the first mask layer is then etched to obtain the pattern.

Abstract: A method of manufacturing a semiconductor device includes providing a carrier, disposing a first pad on the carrier, forming a post on the first pad, and disposing a joint adjacent to the post and the first pad to form a first entire contact interface between the first pad and the joint and a second entire contact interface between the first pad and the post. The first entire contact interface and the second entire contact interface are flat surfaces.

Abstract: An electronic device may include a display system with a pixel array and a catadioptric lens. The display system may include a linear polarizer through which image light from the pixel array passes and a first quarter wave plate through which the light passes after passing through the polarizer. The lens may include a partial mirror, a second quarter wave plate, and a reflective polarizer. A third quarter wave plate may be formed between the linear polarizer and the pixel array to mitigate ghost images. Control circuitry may predict potential ghost images based on the geometry of the lens and data from an image frame. Tone mapping circuitry may adjust contrast of the image frame within a region overlapping the predicted ghost image. The control circuitry may adjust luminance of the image frame outside of the region overlapping the predicted ghost image.

Abstract: An interfacial layer is provided that binds a hydrophilic interlayer dielectric to a hydrophobic gap-filling dielectric. The hydrophobic gap-filling dielectric extends over and fill gaps between devices in an array of devices disposed between two metal interconnect layers over a semiconductor substrate and is the product of a flowable CVD process. The interfacial layer provides a hydrophilic upper surface to which the interlayer dielectric adheres. Optionally, the interfacial layer is also the product of a flowable CVD process. Alternatively, the interfacial layer may be silicon nitride or another dielectric that is hydrophilic. The interfacial layer may have a wafer contact angle (WCA) intermediate between a WCA of the hydrophobic dielectric and a WCA of the interlayer dielectric.

Abstract: A lighting module, an electronic device, and a display panel are provided. The lighting module includes a carrier, a first metal circuit layer, a first transparent conductive layer, a first insulating layer, a second transparent conductive layer, a second metal circuit layer, a bonding structure layer, and a plurality of lighting units. The bonding structure layer is configured to allow the second metal circuit layer to be well bonded to the first insulating layer, so that a resistance value of the lighting module is decreased, and a pressure drop is reduced.

Abstract: A directional patterning method includes following steps. A substrate is provided with a mask layer thereon, and the mask layer has at least one opening pattern therein. A cyclic deposition and etching process is performed to increase a length of the at least one opening pattern.

Abstract: In a method of forming a pattern, a photo resist layer is formed over an underlying layer, the photo resist layer is exposed to an actinic radiation carrying pattern information, the exposed photo resist layer is developed to form a developed resist pattern, a directional etching operation is applied to the developed resist pattern to form a trimmed resist pattern, and the underlying layer is patterned using the trimmed resist pattern as an etching mask.

Abstract: A device package includes a first die comprising a semiconductor substrate; an isolation layer on the semiconductor substrate, wherein the isolation layer is a first dielectric material; a first dummy via penetrating through the isolation layer and into the semiconductor substrate; a bonding layer on the isolation layer, wherein the bonding layer is a second dielectric material that has a smaller thermal conductivity than the first dielectric material; a first dummy pad within the bonding layer and on the first dummy via; a dummy die directly bonded to the bonding layer; a second die directly bonded to the bonding layer and to the first dummy pad; and a metal gap-fill material between the dummy die and the second die.

Abstract: The invention is generally related to an insert for being embedded in a silicone hydrogel contact lens. The insert is made of a crosslinked materials which are rigid in dry state at room temperature (from about 22° C. to about 26° C.), have a high oxygen permeability and a high refractive index in fully hydrated state, and can become softer at a temperature great than 32° C. Such materials are useful for making inserts in embedded contact lenses for correcting corneal astigmatism, presbyopia, and color blindness lenses and for imparting photochromic characteristics to the lenses. The invention is also related to a method for making embedded silicone hydrogel contact lenses comprising an insert of the invention therein and to embedded silicone hydrogel contact lenses comprising an insert of the invention therein.

Abstract: A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

Abstract: A beam splitting and combining device includes a first prism, a second prism and a first optical film. The first prism includes a first surface, a second surface and a third surface. The second prism includes a fourth surface, a fifth surface and a sixth surface. The fifth surface and the second surface are attached to each other. The first optical film is formed between the second surface and the fifth surface by coating. A beam in a first range of wavelengths is configured to pass through the first surface, the second surface, the first optical film, the fifth surface and the sixth surface in order or in reverse order, or is configured to pass through the first surface and the third surface in order or in reverse order.

Abstract: An approach is provided for a gaming overlay application to provide automatic in-game subtitles and/or closed captions for video game applications. The overlay application accesses an audio stream and a video stream generated by an executing game application. The overlay application processes the audio stream through a text conversion engine to generate at least one subtitle. The overlay application determines a display position to associate with the at least one subtitle. The overlay application generates a subtitle overlay comprising the at least one subtitle located at the associated display position. The overlay application causes a portion of the video stream to be displayed with the subtitle overlay.

Abstract: A method of manufacturing a semiconductor device including operations of forming a first hard mask over an underlying layer on a substrate by a photolithographic and etching method, forming a sidewall spacer pattern having a first sidewall portion and a second sidewall portion on opposing sides of the first hard mask, etching the first sidewall portion, etching the first hard mask and leaving the second sidewall portion bridging a gap of the etched first hard mask, and processing the underlying layer using the second hard mask.

Abstract: A structure includes trigger control circuitry for an SCR including: a first transistor having two P-type semiconductor terminals connected to an Nwell and a Pwell of the SCR; a second transistor having two N-type semiconductor terminals connected to the Pwell and ground; and, optionally, an additional transistor having two P-type semiconductor terminals connected to the Nwell and ground. Control terminals of the transistors receive the same control signal (e.g., RST from a power-on-reset). When a circuit connected to the SCR for ESD protection is powered on, ESD risk is limited so RST switches to high. Thus, the first transistor and optional additional transistor turn off and the second transistor turns on, reducing leakage. When the circuit is powered down, the ESD risk increases so RST switches to low. Thus, the first transistor and optional additional transistor turn on and the second transistor turns off, lowering the trigger voltage and current.