Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

Abstract: A method for semiconductor manufacturing includes providing a substrate and a patterning layer over the substrate; forming a hole in the patterning layer; applying a first directional etching along a first direction to inner sidewalls of the hole; and applying a second directional etching along a second direction to the inner sidewalls of the hole, wherein the second direction is different from the first direction.

Abstract: Methods are disclosed herein for patterning integrated circuit devices, such as fin-like field effect transistor devices. An exemplary method includes forming a material layer that includes an array of fin features, and performing a fin cut process to remove a subset of the fin features. The fin cut process includes exposing the subset of fin features using a cut pattern and removing the exposed subset of the fin features. The cut pattern partially exposes at least one fin feature of the subset of fin features. In implementations where the fin cut process is a fin cut first process, the material layer is a mandrel layer and the fin features are mandrels. In implementations where the fin cut process is a fin cut last process, the material layer is a substrate (or material layer thereof), and the fin features are fins defined in the substrate (or material layer thereof).

Abstract: A totem-pole PFC and a current-sampling unit of the totem-pole PFC are provided. The totem-pole PFC is electrically connected to an AC power source and a DC-to-DC converter, and is electrically connected to a load through the DC-to-DC converter. The current-sampling unit has a first sampling switch and a second sampling switch. The first sampling switch and the second sampling switch are controlled to be turned on and turned off so that a magnetizing current flows through the magnetizing inductor when a magnetizing inductor is magnetized and a demagnetizing current does not flow through the sampling resistor when the magnetizing inductor is demagnetized, thereby increasing the demagnetization efficiency and overcoming superimposed operations to improve current detection and increase conversion efficiency of the power conversion.

Abstract: A technique for patterning a workpiece such as an integrated circuit workpiece is provided. In an exemplary embodiment, the method includes receiving a workpiece having a material layer disposed on a substrate. A first set of fins is formed on the material layer, and a second set of fins is formed on the material layer interspersed between the first set of fins. The second set of fins have a different etchant sensitivity from the first set of fins. A first etching process is performed on the first set of fins and configured to avoid substantial etching of the second set of fins. A second etching process is performed on the second set of fins and configured to avoid substantial etching of the first set of fins. The material layer is etched to transfer a pattern defined by the first etching process and the second etching process.

Abstract: A method of manufacturing a semiconductor device includes depositing a first material on a substrate, depositing on the substrate a second material that has an etch selectivity different from an etch selectively of the first material, depositing a spacer material on the first and second material, and etching the substrate using the spacer material as an etch mask to form a fin under the first material and a fin under the second material.

Abstract: A feed forward controlling circuit is used to perform a feed forward controlling method to restrain ripple of the output voltage in a power converter. The power converter is controlled by a control signal outputted from an output terminal of a controller. The method includes steps of: receiving an output voltage from an output terminal of a voltage converter; attenuating the output voltage to generate an electrical signal; acquiring a DC signal from the electrical signal; and obtaining a ripple compensation signal in accordance with the electrical signal and the DC signal to output to an output terminal of a controller. The output terminal of the controller outputs a control signal to control the power converter.

Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof.

Abstract: Exemplary methods of patterning a device layer are described, including operations of patterning a protector layer and forming a first opening in a first patterning layer to expose a first portion of the protector layer and a first portion of the hard mask layer, which are then are exposed to a first etch to form a first opening in the first portion of the hard mask layer. A second opening is formed in a second patterning layer to expose a second portion of the protector layer and a second portion of the hard mask layer. The second portion of the protector layer and the second portion of the hard mask layer are exposed to an etch to form a second opening in the second portion of the hard mask layer. Exposed portions of the device layer are then etched through the first opening and the second opening.

Abstract: An operation method of a memory cell includes steps of applying a pre pulse before a read pulse is applied, wherein the pre pulse is larger than a maximum threshold voltage or less than a lowest threshold voltage.

Abstract: A method, of manufacturing fins for a semiconductor device which includes Fin-FETs, includes: forming a structure including a semiconductor substrate and capped semiconductor fins, the capped semiconductor fins being organized into at least first and second sets, with each member of the first set having a first cap with a first etch sensitivity, and each member of the second set having a second cap with a second etch, the second etch sensitivity being different than the first etch sensitivity; removing selected members of the first set and selected members of the second set from the structure.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first flowable-material (FM) layer over a substrate. A top surface of the first FM layer in a first region is higher than a top surface of the first FM layer in a second region. The method also includes forming a sacrificial plug to cover the first FM layer in the first region, forming a second FM layer over the sacrificial plug in the first region and over the first FM layer in the second region, performing a first recessing process such that the second FM layer is removed in the first region and performing a second recessing process on the second FM layer in the second region while the first FM layer is protected by the sacrificial plug in the first region.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first flowable-material (FM) layer over a substrate. A top surface of the first FM layer in a first region is higher than a top surface of the first FM layer in a second region. The method also includes forming a sacrificial plug to cover the first FM layer in the first region, forming a second FM layer over the sacrificial plug in the first region and over the first FM layer in the second region, performing a first recessing process such that the second FM layer is removed in the first region and performing a second recessing process on the second FM layer in the second region while the first FM layer is protected by the sacrificial plug in the first region.

Abstract: A method includes providing a substrate; forming mandrel patterns over the substrate; and forming spacers on sidewalls of the mandrel patterns. The method further includes removing the mandrel patterns, thereby forming trenches that are at least partially surrounded by the spacers. The method further includes depositing a copolymer material in the trenches, wherein the copolymer material is directed self-assembling; and inducing microphase separation within the copolymer material, thereby defining a first constituent polymer surrounded by a second constituent polymer. The mandrel patterns have restricted sizes and a restricted configuration. The first constituent polymer includes cylinders arranged in a rectangular or square array.

Abstract: A method includes forming a first layer over a substrate; forming a patterned photoresist layer over the first layer; applying a solution over the patterned photoresist layer to form a conformal layer over the pattern photoresist layer, wherein the conformal layer further includes a first portion over a top surface of the patterned photoresist layer and second portion extending along sidewalls of the patterned photoresist layer; selectively removing the first portion of the conformal layer formed over the top surface of the patterned photoresist layer; andselectively removing the patterned photoresist layer thereby leaving the second portion of the conformal layer.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming mandrels over a material layer and forming spacers along sidewalls of mandrels, forming a patterned hard mask to cover a first region, depositing a filling layer in a second region while the patterned hard mask covers the first region. A space between two adjacent spacers in the second region is filled in by the filling layer. The method also includes recessing the filling layer to form a filling block in the space between two adjacent spacers in the second region, removing the patterned hard mask, removing mandrels and etching the material layer by using spacers and the filling block as an etch mask to form material features in the first region and the second region, respectively.

Abstract: A feed forward controlling circuit and a method for voltage ripple restraint are provided. The feed forward controlling circuit is used to perform the feed forward controlling method. The feed forward controlling method is used to restrain ripple of the output voltage in a power converter. The power converter is controlled by a control signal outputted from an output terminal of a controller. The method includes steps of: receiving an output voltage from an output terminal of a voltage converter; attenuating the output voltage to generate an electrical signal; acquiring a DC signal from the electrical signal; and obtaining a ripple compensation signal in accordance with the electrical signal and the DC signal to output to an output terminal of a controller. The output terminal of the controller outputs a control signal to control the power converter.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming mandrels over a material layer and forming spacers along sidewalls of mandrels, forming a patterned hard mask to cover a first region, depositing a filling layer in a second region while the patterned hard mask covers the first region. A space between two adjacent spacers in the second region is filled in by the filling layer. The method also includes recessing the filling layer to form a filling block in the space between two adjacent spacers in the second region, removing the patterned hard mask, removing mandrels and etching the material layer by using spacers and the filling block as an etch mask to form material features in the first region and the second region, respectively.

Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first patterned hard mask over a material layer. The first patterned hard mask defines an opening. The method also includes forming a direct-self-assembly (DSA) layer having a first portion and a second portion within the opening, removing the first portion of the DSA layer, forming spacers along sidewalls of the second portion of the DSA layer and removing the second portion of the DSA layer. The spacers form a second patterned hard mask over the material layer.

Abstract: A method of forming fins on a substrate is provided. The method comprises depositing first fin spacers comprising first fin spacer material and second fin spacers comprising second fin spacer material on a plurality of locations on a substrate having a hard mask above the substrate's semiconductor material, wherein the first fin spacers comprise desired first fin spacers and dummy first fin spacers and the second fin spacers comprise desired second fin spacers and dummy second fin spacers. The method further comprises forming fins on the substrate under the first fin spacers and the second fin spacers. The fins comprise a plurality of dummy fins and a plurality of desired fins. The dummy fins comprise a plurality of dummy first fins formed under the dummy first fin spacers and a plurality of dummy second fins formed under the dummy second fin spacers.