Abstract: The present invention relates to a method for a processor and a computer system to enter system management mode (SMM). The method is applied to the processor, which includes at least one logical core. The method includes entering the SMM in response to a system management interrupt (SMI), storing current state information to a corresponding state save area; setting operation mode to target operating mode, and executing the SMI handler under the target operating mode. The address of the state save area, the address of the core configuration information memory space, and the address of the SMI handler can be determined directly. Each logical core may enter the target operating mode directly through hardware setting every time after entering the SMM, and thus does not need to perform a fixed operation of mode switching when executing the SMI handler, which may improve the execution efficiency of the SMI handler.

Abstract: The present application relates to the technical field of system management mode (SMM), and in particular it relates to a control method, a processor, and a computer system for system management mode. The method is applied to a processor. The processor includes at least one logical core. The method performs an initialization setting before each logical core enters system management mode. The initialization setting includes: allocating system management random access memory (SMRAM) required in the SMM to each logical core; and storing addresses related to the SMRAM of each logical core into at least one model-specific register MSR. There is no need to set SMRAM for each logical core serially. This shortens the time spent on initialization in the SMM and improves the execution efficiency of initialization.

Abstract: A computer system with a hybrid architecture processor that provides both first-type and second-type cores is shown. In response to execution of an application, an operating system running on the hybrid architecture processor evaluates core-change indicators corresponding to the application, to change the core executing the application from the first-type core to the second-type core, or vice versa, based on the core-change indicators, to continue execution of the application.

Abstract: A computer system with a hybrid architecture processor that provides both first-type and second-type cores is shown. The second-type core uses special instructions not supported by the first-type core, or supported by the first-type core in a semantically changed manner. In response to the first-type core executing an application that has any of the special instructions, the application is migrated to the second-type core for execution.

Abstract: An instruction simulation device and a method thereof are provided. The instruction simulation device includes a processor. The processor includes an instruction decoder which generates format information of a ready-for-execution instruction. The processor determines whether the ready-for-execution instruction currently executed by the processor is a compatible instruction or an extended instruction based on the format information of the ready-for-execution instruction. If the ready-for-execution instruction is an extended instruction under the new instruction set or the extended instruction set, the processor converts the ready-for-execution instruction into a simulation program corresponding to the extended instruction, and simulates an execution result of the ready-for-execution instruction by executing the simulation program. The simulation program is composed of at least one compatible instructions of the processor.

Abstract: A computer system with a system memory encryption and decryption function is shown, which uses global context isolated keys to encrypt and decrypt data of a system memory that is coupled to the processor. In particular, the processor identifies the keys using key identification codes (KeyID), and each key identification code includes a global context identification code (GCID).

Abstract: A computer system with a processor having an encryption and decryption engine is shown. The encryption and decryption engine includes a key table, which is provided for encryption and decryption of the system memory. In response to a platform setting instruction, the processor reads a key identification code from a key identification code register, and reads control parameters from a control parameter register. Based on the control parameters, the processor manages a key, associated with the key identification code, in the key table.

Abstract: A computer system with data encryption and decryption on system memory is shown. The computer system has a system memory storing data, and a processor coupled to the system memory. The processor has key registers storing multiple keys. Based on the access address on the system memory, the processor selects a target key from the key registers, to apply the target key to perform data encryption and decryption on the system memory.

Abstract: The present invention relates to the field of IPC C08L69, and more specifically relates to a chemical-resistant polycarbonate composition and a preparation method therefor. The composition includes 15-30 parts of a polycarbonate-polysiloxane copolymer, 50-90 parts of a bisphenol A polycarbonate, 20-40 parts of a polycarbonate master batch, and 0.01-0.1 part of an additive; and the composition includes the polycarbonate-polysiloxane copolymer having a ratio of a polysiloxane block of 15-30 wt %. By adding an organic silicon composition SFR 100, a polycarbonate material can be obviously improved in resistance to corrosion of chemical agents without cracking, which can be applied to medical treatment and electronic equipment. An E value (polymerization unit) is 40-100, and a proportion of the polycarbonate-polysiloxane copolymer in the composition is greater than 17.

Abstract: The present invention provides a double-crosslinked fibrin gel, which is a solid hydrogel composed of a network structure with a blocking function and a network structure with an adhesion function, where the network structure with the blocking function is a three-dimensional fibrin network, and the network structure with the adhesion function is a three-dimensional photosensitive gel network; each channel of the photosensitive gel network has a group of the fibrin network inside, and each group of the fibrin network has overall continuity; on the whole, the three-dimensional fibrin network disperses disorderly throughout a surface and an interior of the solid hydrogel. The present invention further provides a raw material composition, a kit for preparing the double-crosslinked fibrin gel, and an application of the kit to prepare an in-situ rapid clotting and hemostatic material.

Abstract: The present disclosure provides a power battery monitoring system and a method. The system includes a battery assembly, N monitoring assemblies and an upper monitoring platform. The N monitoring assemblies are connected in series with each other, and a first monitoring assembly is connected with the upper monitoring platform, wherein the number of sampling channels of each monitoring assembly is M. The power battery monitoring system can segment the battery cells; the number of the battery cells in each segment is M; the battery cells in each segment are connected with a same monitoring assembly; and the N monitoring assemblies acquire sampling data of the battery cells in this segment through the corresponding sampling channel, so as to realize the monitoring of the battery cells in this segment by the upper monitoring platform.

Abstract: A technology flushing a hierarchical cache structure based on a designated key identification code and a designated address. A processor includes a first core and a last level cache (LLC). The first core includes a decoder, a memory ordering buffer, and a first in-core cache module. In response to an Instruction Set Architecture (ISA) instruction that requests to flush a hierarchical cache structure according to a designated key identification code and a designated address, the decoder outputs at least one microinstruction. According to the at least one microinstruction, a flushing request with the designated key identification code and the designated address is provided to the first in-core cache module through the memory ordering buffer, and then the first in-core cache module provides the LLC with the flushing request, so that the LLC flushes its matching cache line which matches the designated key identification code and the designated address.

Abstract: A processor and a method for designating an in-core cache of a hierarchical cache system to perform writing-back and invalidation of cached data are shown. In response to an instruction that is in the instruction set architecture and is executed to designate a designated-level cache within the current core as a target to perform writing-back and invalidation, a decoder of the current core outputs microinstructions. According to the microinstructions, a level-designation request indicating the designated-level cache within the current core is transferred to the hierarchical cache system through the memory order buffer. In response to the level-designation request, the hierarchical cache system recognizes cache lines related to the designated-level cache of the current core, writes modified cache lines (which are obtained from the recognized cache lines) back to the system memory, and then invalidates all the recognized cache lines from the hierarchical cache system.

Abstract: A battery equalization method, comprising: step A1: according to acquired data information of a battery, determining that the battery is a balanceable battery or a replaceable battery; step A2: charging and discharging a module in the balanceable battery; step A3: monitoring the voltage of each cell in the module and the temperature of the module; and step A4: shunting the equalization current between the cells, so as to ensure that the voltage difference between the cells does not exceed a first preset voltage difference value. Further disclosed is a battery equalization system. By means of the method, a battery can be effectively discriminated, thereby improving the equalization effect, shortening the equalization time, and thus improving the equalization efficiency.

Abstract: A battery pack detection connection apparatus includes: a communication module used for communicating with a vehicle communication interface and a battery pack; a microcontroller unit used for extracting change features of an externally inputted signal, performing signal feature reconstruction on the extracted change features of the signal, and transmitting the reconstructed signal features to a function generator or signal module; at least one function generator used for outputting, according to the reconstructed signal features, a first-type waveform signal exchanged between a vehicle and the battery pack; and the signal module used for outputting, according to the reconstructed signal features, a second-type waveform signal exchanged between the vehicle and the battery pack. The present apparatus uses the function generator and the signal module to achieve signals required by the battery pack for interaction. The same hardware can be used to match different brands of vehicle models.

Abstract: A computing system with a first instruction of an instruction set architecture (ISA) for direct invalidation, without writing back, in a hierarchical cache structure based on one single designated key identification code, and a second instruction of ISA for direct invalidation, without writing back, in the hierarchical cache structure based on a plurality of designated key identification codes is shown. A decoder transforms the first or second instruction into at least one microinstruction. Based on the at least one microinstruction, one direct invalidation request is provided corresponding to each designated key identification code, to be passed to the hierarchical cache structure through a memory ordering buffer. For each direct invalidation request, the cache line write-back and invalidation regarding a designated key identification code is performed on a last-level cache first, and then is performed on the in-core cache modules.

Abstract: A processor and a method for designating a demotion target to demote the demotion target from an in-core cache structure to an out-of-core cache structure is shown. In response to a cache data demotion instruction supported by an instruction set architecture, a first core of a processor operates a decoder to decode the cache data demotion instruction into microinstructions. According to the microinstructions, a demotion target designation request is transferred to a last-level cache (LLC) through a memory order buffer to drive the LLC to query an out-of-core cache table. According to the demotion target's cache status in the first core obtained from the out-of-core cache table, the LLC outputs a snoop request to the first core to snoop on the demotion target and demote the demotion target from the in-core cache structure of the first core to the LLC.

Abstract: An instruction execution method for a microprocessor is provided. The microprocessor includes a model specific register (MSR). And, the instruction execution method includes the following steps. A target instruction is received using an instruction cache. The target instruction is decoded using an instruction translator to determine whether the target instruction is a specific instruction is a specific instruction. When the target instruction is the specific instruction, a model specific register index of the target instruction is obtained to directly read or write the model specific register.

Abstract: An instruction configuration and execution method includes the following steps. A target instruction is received through an instruction cache. The target instruction is decoded by an instruction translator. It is determined whether the target instruction has the authority to read or write the model specific register in an unprivileged state. It is determined whether the model specific register index of the specific instruction corresponds to a specific model specific register, so as to order the microprocessor to perform an instruction serialization operation.

Abstract: A computer-implemented method for generating an improved map of field anomalies using digital images and machine learning models is disclosed.