Abstract: A method for executing new instructions includes the following steps: receiving an instruction and determining whether the received instruction is a new instruction. When the received instruction is the new instruction, entering a system management mode, and simulating the execution of the received instruction by executing at least one old instruction in the system management mode.

Abstract: A method for converting instructions is provided. The method is used in a processor and includes: receiving an instruction; generating an unknown instruction exception when the received instruction is an unknown instruction; in response to the unknown instruction exception, entering a system management mode; and in the system management mode, executing the following steps through a conversion program: determining whether the received instruction is a new instruction; and simulating the execution of the received instruction by executing at least one old instruction when the received instruction is a new instruction.

Abstract: A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, the processor executes the following steps through a conversion program: determining whether the received instruction is a new instruction; and converting the received instruction into at least one old instruction when the received instruction is a new instruction; and simulating the execution of the received instruction by executing the at least one old instruction.

Abstract: A method for executing new instructions includes the following steps. An instruction is received. A determination is made as to whether the received instruction is a new instruction. When the received instruction is the new instruction, a emulation flag is generated. The emulation flag is a first value. A system management interrupt is generated according to the emulation flag. In response to the system management interrupt, entering the system management mode and simulating the execution of the received instruction in the system management mode to generate a simulation execution result. The simulation execution result is stored in a system management memory.

Abstract: A method for executing new instructions is provided. The method is used in a processor and includes: receiving an instruction; when the received instruction is an unknown instruction, executing a conversion program by an operating system, wherein the conversion program executes the following steps: determining whether the received instruction is a new instruction; converting the received instruction into at least one old instruction when the received instruction is a new instruction; and executing the at least one old instruction.

Abstract: A continuous slurry-bed tank reactor, comprising a tank reactor body, an agitator, and tubular separation membranes. A method of using the continuous slurry-bed tank reactor comprising adding a catalyst, feeding reactants, stopping feeding the reactants, starting a heating system, changing directions of the reactants flowing through the tubular separation membranes.

Abstract: A multi-chip system and a cache processing method are provided. The multi-chip system includes multiple chips. Each chip includes multiple clusters, a crossbar interface, and a snoop system. Each cluster corresponds to a local cache. The crossbar interface is coupled to the clusters and a crossbar interface of another chip. The snoop system is coupled to the crossbar interface and performs unidirectional transmission with the crossbar interface. The snoop system includes a snoop table module and multiple trackers. The snoop table module includes a shared cache, which records a snoop table. Multiple trackers are coupled to the snoop table module, query the snoop table in the shared cache according to a memory access request initiated by one of clusters, and update the snoop table according to a query result. The snoop table corresponds to a storage structure of the local cache corresponding to the clusters in all chips.

Abstract: The disclosure provides a data prefetching auxiliary circuit, a data prefetching method, and a microprocessor. The data prefetching auxiliary circuit includes a stride calculating circuit, a comparing module, a stride selecting module, and a prefetching output module. The stride calculating circuit receives an access address to calculate and provide a stride. The comparing module receives the access address and the stride, generates a reference address based on a first multiple, the access address and the stride, determines whether the reference address matches any of a plurality of history access addresses, and generates and outputs a hit indicating bit value. The stride selecting module receives the hit indicating bit value, and determines whether to output the hit indicating bit value based on a prefetch enabling bit value. The prefetching output module determines a prefetch address according to the output of the stride selecting module.

Abstract: An endoscope motherboard, an endoscope and a detection method are provided. The endoscope motherboard is connected to a terminal and a camera module. The endoscope motherboard includes a communication interface, a wireless communication module and an adapter board. The communication interface and the wireless communication module are connected to the adapter board. The adapter board is connected to the camera module. The communication interface or the wireless communication module is connected to the terminal. The adapter board includes a detection module and a gating switch. The detection module detects a status of connection between the communication interface or the wireless communication module and the terminal and transmit a signal to the gating switch according to the status of connection. The gating switch connects the camera module to the communication interface or the wireless communication module according to the signal.

Abstract: A host interconnection device includes a serializing module, an analysis module, an arbitration module, a data-writing tracking module, and a data-reading tracking module. The serializing module serializes at least one first read/write request generated by at least one processing module and a second read/write request generated by a chipset module, and outputs the first read/write request or the second read/write request. The analysis module generates analysis information according to the first read/write request or the second read/write request. The arbitration module arbitrates the analysis information and snoop information, and generates arbitration information. The data-writing tracking module performs a data-writing tracking operation on the arbitration information to generate a first snoop request, a data-writing indication, and a data-writing request.

Abstract: The disclosure relates to a process for continuously producing polyoxymethylene dimethyl ethers at low temperature, pertains to the technical field of polyoxymethylene dimethyl ether preparation processes, and solves the technical problem of continuous production of polyoxymethylene dimethyl ether. A membrane separation element with precisely controlled pores in membrane is used to realize a direct separation of the feedstocks from the catalyst within the reactor, and effectively reduce the permeation resistance of the separation membrane tube. By oppositely switching the flowing direction of liquid reaction materials, the adhesion of the catalyst to the separation membrane tube is inhibited, and some particles stuck in separation membrane tube are removed, which ensures the continuous operation of the reaction process and allows a molecular sieve catalyst to exhibit its advantage of long catalytic life.

Abstract: The present disclosure provides a cache system and an operating method thereof. The system includes an upper-level cache unit and a last level cache (LLC). The LLC includes a directory, a plurality of counters, and a register. The directory includes a status indicator recording a utilization status of the upper-level cache unit to the LLC. The counters are used to increase or decrease a counting value according to a variation of the status indicator, record an access number from the upper-level cache unit, and record a hit number of the upper-level cache unit accessing the LLC. According to the counting value, the access number, and the hit number, the first parameters of the register are controlled, so as to adjust a utilization strategy to the LLC.

Abstract: Live objects in heap memory exceeding a threshold size and that have not been recently accessed are compressed or offloaded to secondary memory or storage. Compressing or offloading an object can further be based on how old the object is, which can be determined based on how many garbage collections the object has survived. Objects comprising references to other objects can be split into two sub-objects, one containing value fields that is compressed or offloaded and one containing reference fields that remains uncompressed in heap memory. Heap memory can undergo compaction after objects are compressed or offloaded. Compression accelerators can be used for compression and the decision of whether to compress or offload an object can be based on accelerator throughput, latency, availability, as well as other computing system metrics or characteristics. The compressing and offloading of objects and subsequent compaction can make more heap memory available for object allocation.

Abstract: A microprocessor for neural network computing having a mapping table, a microcode memory, and a microcode decoding finite-state machine (FSM) is disclosed. According to the mapping table, a macroinstruction is mapped to an address on the microcode memory. The microcode decoding FSM decodes contents which are retrieved from the microcode memory according to the address, to get microinstructions involving at least one microinstruction loop that is repeated to operate a datapath to complete the macroinstruction.

Abstract: The embodiments of the present invention relate to the field of vehicle diagnosis technologies, and specifically disclose a communication method and apparatus, and a related device.

Abstract: The present disclosure provides a cache system and an operating method thereof. The system includes an upper-level cache unit and a last level cache (LLC). The LLC includes a directory, a plurality of counters, and a register. The directory includes a status indicator recording a utilization status of the upper-level cache unit to the LLC. The counters are used to increase or decrease a counting value according to a variation of the status indicator, record an access number from the upper-level cache unit, and record a hit number of the upper-level cache unit accessing the LLC. According to the counting value, the access number, and the hit number, the first parameters of the register are controlled, so as to adjust a utilization strategy to the LLC.

Abstract: The disclosure provides a data prefetching auxiliary circuit, a data prefetching method, and a microprocessor. The data prefetching auxiliary circuit includes a stride calculating circuit, a comparing module, a stride selecting module, and a prefetching output module. The stride calculating circuit receives an access address to calculate and provide a stride. The comparing module receives the access address and the stride, generates a reference address based on a first multiple, the access address and the stride, determines whether the reference address matches any of a plurality of history access addresses, and generates and outputs a hit indicating bit value. The stride selecting module receives the hit indicating bit value, and determines whether to output the hit indicating bit value based on a prefetch enabling bit value. The prefetching output module determines a prefetch address according to the output of the stride selecting module.

Abstract: The present invention provides a method and an apparatus for configuring an automobile diagnostic function, and an automobile diagnostic device. The method for configuring an automobile diagnostic function includes: obtaining first function configuration information from a server, the first function configuration information including an identifier of at least one automobile diagnostic function; determining an automobile diagnostic function group based on the first function configuration information; and granting use permission of the automobile diagnostic function group in an automobile diagnostic application program. Function configuration information is obtained from the server and then an automobile diagnostic function supported by a product is configured, thereby improving flexibility of automobile diagnostic function configuration and reducing product development and maintenance costs.

Abstract: A multi-chip system and a cache processing method are provided. The multi-chip system includes multiple chips. Each chip includes multiple clusters, a crossbar interface, and a snoop system. Each cluster corresponds to a local cache. The crossbar interface is coupled to the clusters and a crossbar interface of another chip. The snoop system is coupled to the crossbar interface and performs unidirectional transmission with the crossbar interface. The snoop system includes a snoop table module and multiple trackers. The snoop table module includes a shared cache, which records a snoop table. Multiple trackers are coupled to the snoop table module, query the snoop table in the shared cache according to a memory access request initiated by one of clusters, and update the snoop table according to a query result. The snoop table corresponds to a storage structure of the local cache corresponding to the clusters in all chips.

Abstract: The present application discloses a display panel and a display device. The display panel includes: a common electrode layer including a plurality of columns of first common electrodes, wherein each column of the plurality of columns of the first common electrodes includes a plurality of touch electrodes insulated from each other; and a driving module. Each of the plurality of touch electrodes is electrically connected to the driving module through one or more touch leads. A number of the touch leads corresponding to each of or adjacent ones of the plurality of touch electrodes gradually increases along a direction away from the driving module.