Abstract: Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a 3D semiconductor device includes: an array of vertical transistors each comprising a semiconductor body extending in a vertical direction; a plurality of word lines each extending in a first lateral direction, wherein each word line is shared by a row of the vertical transistors arranged along the first lateral direction; and a plurality of bit lines each extending in a second lateral direction perpendicular to the first lateral direction; wherein the semiconductor bodies are further arranged along a third lateral direction different from the first lateral direction and the second lateral direction.

Abstract: In various examples, a technique for evaluating a robotics system includes receiving a configuration document including at least descriptions of a robotics system, an operating environment, and one or more tasks, and instantiating one or more instances of a test stack operating on a robotics platform, wherein a number of the one or more instances is determined based at least on the one or more tasks. The technique also includes generating one or more items of test data based at least on the execution of the one or more tasks via the test stack, executing a set of metrics plugins to calculate one or more metric values based at least on the one or more items of test data, and collecting at least the one or more metric values for display to a user.

Abstract: Methods, systems, and devices for wireless communication are described. A wireless device may generate a set of shaping bits based on performing a constellation shaping operation on a set of information bits. Further, the wireless device may perform a first error correction encoding operation based on the set of shaping bits and a second error correction encoding operation based on the set of information bits to generate a first set of coded bits and a second set of coded bits, respectively. Moreover, the wireless device may transmit a control message that indicates an offset that identifies a first resource mapping for the first set of coded bits and a second resource mapping for the second set of coded bits and transmit the first set of coded bits in accordance with the first resource mapping and the second set of coded bits in accordance with the second resource mapping.

Abstract: A semiconductor device includes a peripheral circuit structure. The peripheral circuit structure includes a periphery circuit disposed on a substrate and a first interconnection structure disposed on the periphery circuit. The first interconnection structure includes a first conductive structure extending in a first direction, a second conductive structure extending in the first direction, a third conductive structure extending in the first direction, wherein the second conductive structure is disposed between the first conductive structure and the third conductive structure in a second direction perpendicular to the first direction, and a contact structure extending in the second direction in direct contact with the first conductive structure and the third conductive structure.

Abstract: A system, method, and computer-program product includes obtaining a plurality of digital event records associated with a plurality of online subscriber environments; extracting, from the plurality of digital event records, user-identity-related attributes; constructing, for the plurality of subscriber environments, a global identity graph; automatically detecting indirect digital threat associations between given sets of user account node data objects within the global identity graph by executing a multi-hop traversal instruction on the global identity graph; generating, for each user account node data object in the global identity graph, a respective threat indicator based at least in part on the direct digital threat associations and detected indirect digital threat associations linked to the associated digital user account; and executing at least one workflow rule that modifies operation of a target digital user account associated with a target user account node data object based at least in part on the re

Abstract: A quantum computing circuit is disclosed herein. An example quantum computing circuit includes a first chip with at least one qubit thereon. The quantum computing circuit also includes a second chip with at least other quantum circuit elements other than qubits thereon. The first chip and the second chip are stacked together in a flip-chip configuration and attached to each other with bump bonding that includes bonding bumps.

Abstract: A device control method and an electronic device are provided. The method includes: A first electronic device establishes a connection to a second electronic device in response to a preset gesture operation; the second electronic device returns first information to the first electronic device, where the first information includes related information of the second electronic device and/or related information of a first application and/or a first function on the second electronic device; and the first electronic device displays a control interface based on the first information, where the control interface is for controlling the second electronic device. In this manner, a user performs the preset gesture operation on the first electronic device, to invoke the first information of the second electronic device, to display the control interface for controlling the second electronic device. In this way, an operation is convenient, and user experience is good.

Abstract: The display panel has a display area and a peripheral area outside the display area; the display area is provided with pixel circuits; the peripheral area is provided with a peripheral circuit; at least one peripheral circuit includes a plurality of circuit groups spaced apart along a column direction, a trigger signal line, and at least one test line; one of the circuit groups includes a plurality of shift registers cascaded along the column direction; any row of the pixel circuits is connected to at least one of the shift registers through a scanning line; a first shift register of each circuit group is connected to one trigger signal line, and there are different trigger signal lines connected to different circuit groups; a last shift register of at least one of the circuit groups is connected to one test line.

Abstract: The present invention belongs to the technical field of preparing isocyanate derivatives, and particularly relates to a storage-stable polyisocyanate composition and a preparation method therefor. The method comprises: in the presence of a catalyst system, subjecting an isocyanate monomer to a polymerization reaction; terminating the reaction after a suitable conversion rate is reached, so as to obtain a polyisocyanate reaction solution; and then performing heat treatment on the obtained polyisocyanate reaction solution to obtain a heat-treated polyisocyanate mixture, wherein the heat treatment temperature is 10-30° C. higher than the heat-sensitive temperature of the obtained polyisocyanate product, and the heat treatment time is 5-30 min; and then performing separation treatment on the heat-treated polyisocyanate mixture. When the polyisocyanate composition of the present invention is stored at 50° C.

Abstract: Embodiments of the present disclosure provide a video generation method, a model determination method, a device, a storage media, a computer program product and a computer program. The video generation method includes: acquiring a target audio; generating an image sequence according to characteristic information of the target audio and an image generation model, wherein the image generation model is used for generating a corresponding image according to a randomly input vector; and combining the target audio and the image sequence to generate a target video corresponding to the target audio.

Abstract: A method for forming a 3D memory device includes forming an array wafer based on a first substrate having at least one cell region for forming a plurality of memory cells and at least one string structure region for forming a string structure; forming a first complementary metal-oxide-semiconductor (CMOS) wafer based on a second substrate having at least one string driver region corresponding to the at least one string structure region, and at least one page buffer high-voltage (HV) circuit region corresponding to the at least one cell region; forming a second CMOS wafer based on a third substrate having at least one page buffer region corresponding to the at least one cell region; and forming the 3D memory device based on the array wafer, the first CMOS wafer, and the second CMOS wafer stacked together.

Abstract: A combination heat dissipation unit includes a vapor chamber defining an airtight chamber filled with a working fluid and at least one heat pipe having an open end. The vapor chamber is provided at an upper side with at least one through hole communicable with the airtight chamber and on a lower inner side with a first wick structure. At least one annular element is provided in the airtight chamber corresponding to the through hole. The open end of the heat pipe is correspondingly inserted into the through hole to enter the airtight chamber and contact with the annular element to be fixedly supported thereon. With these arrangements, the path and time for the working fluid to flow from the heat pipe back to the vapor chamber are largely shortened, dry burning in the vapor chamber is avoided, and two-phase heat exchange efficiency of the heat dissipation unit is upgraded.

Abstract: Example three-dimensional (3D) memory devices, methods, and memory systems for connecting vertical transistors and capacitors using connect structures are disclosed. One example method includes forming a first structure that includes multiple vertical transistors. A connect layer is formed over the first structure. The connect layer is etched to form connect structures, where each of the connect structures is coupled to a corresponding one of the vertical transistors. Multiple capacitors are formed over the connect layer, where each of the plurality of capacitors is coupled to a respective connect structure.

Abstract: This application relates to a loudspeaker and an electronic device. In one example, the loudspeaker includes a cone frame, a first sounding unit, a second sounding unit, and an elastic suspension. The first sounding unit includes a magnetic circuit structure mounted on the cone frame, an annular vibrating diaphragm, and a voice coil connected to the annular vibrating diaphragm. The second sounding unit is arranged coaxially with the first sounding unit, where the second sounding unit is mounted in the middle of a side that is of the magnetic circuit structure and that faces the annular vibrating diaphragm. The elastic suspension is configured to elastically support the voice coil and the annular vibrating diaphragm on the cone frame.

Abstract: Disclosed is an aliphatic polyisocyanate composition, wherein the molar ratio of an iminooxadiazinedione structure to an isocyanurate structure is 0.01-0.8:1, and the molar ratio of an iminooxadiazinedione structure in a polymer larger than three molecules to the iminooxadiazinedione structure in the composition is 0.2-0.8:1. Provided are a method for preparing the aliphatic polyisocyanate composition, and a coating composition. The aliphatic polyisocyanate composition has both a lower viscosity and a better crosslinking property. The composition can significantly reduce the usage amount of a solvent when used in a coating composition, is more environmentally friendly and also has a better paint film property. The preparation method has a simple process and mild conditions, is easy to operate and control, and is suitable for industrial scale production.

Abstract: An electrode assembly includes a plurality of electrode plates and a separator disposed between two of the electrode plates of opposite polarities. At least one of the electrode plates has a plurality of protrusions. The protrusions have a height H (?m). When 20?H?80 is satisfied, the protrusions can provide strong support to improve electrolyte infiltration effect. The separator includes a base film and a ceramic layer connected to the base film, and the ceramic layer is provided on a side of the base film along a thickness direction. The base film has a puncture strength C (gf), the ceramic layer has a thickness D1 (?m), C satisfies 100?C?500, and D1 satisfies 1?D1?6.

Abstract: A semiconductor device and methods for forming the same are provided. The method includes: forming a plurality of first trenches having a first width during forming a plurality of grooves having a second width less than the first width, each of the plurality of first trenches and the plurality of grooves extending laterally along a first lateral direction and vertically in an upper portion of a semiconductor layer, the plurality of first trenches and the plurality of grooves being alternatively arranged along a second lateral direction different from the first lateral direction; forming a spacer in each groove, where the spacer is laterally extending along the first lateral direction; and forming two disconnected conductive structures in each first trench, the disconnected conductive structures laterally extending in parallel along the first lateral direction.

Abstract: This application discloses a speaker and an electronic device, including: a first housing with a sound outlet channel; a second housing connected to the first housing; and a speaker unit. After the speaker unit is connected to the first housing, a front cavity and a rear cavity are formed, where the front cavity is connected to the sound outlet channel, and the rear cavity is a sealed cavity. The raw material components of the first housing and the second housing include 50-90 wt % of a polymer composite material and 10-50 wt % of a hollow sphere material. 10-50 wt % of the hollow sphere material is added to the raw material components of the first housing and the second housing.

Abstract: A spring coil system includes a spring coil and a spring coil conveying device. The conveying device includes a push rod and a manipulation member. A notch is provided in an outer circumference of the push rod at a distal end thereof, and the manipulation member is disposed inside the push rod. A proximal end of the manipulation member is located at a proximal end of the push rod, and the manipulation member distally extends along the axis of the push rod to the notch. A spring coil connector is looped through the notch in the conveying device and confined therein by the manipulation member. When a force is applied to the manipulation member to cause it to displace toward the proximal end of the push rod and thereby no longer confine the connector, the connector is allowed to dislodge from the notch, resulting in its detachment.

Abstract: An electrode assembly includes two electrode plates and a separator, at least one electrode plate including a main body portion and corner portions, the main body portion includes main body portion protrusions, a height of the main body portion protrusions is H1 (?m), the corner portion including multiple corner portion protrusions, a height of the corner portion protrusions being H2 (?m), an orthographic projection of the main body portion protrusions and of the corner portion protrusions along a thickness direction of the electrode plate forming a first pattern and a second pattern, an average radial dimension of the first pattern being R1 (mm), an average radial dimension of the second pattern being R2 (mm), satisfying: ?0.2665?H1/1000R1?H2/1000R2?0.0131, the separator including a base film and an adhesive layer, a thickness of the adhesive layer being F (?m), satisfying: 4?H2/F?800.