Abstract: An operating-system-first error handling system includes an operating system subsystem coupled to a BMC device including a shared memory subsystem, and to a reserved memory subsystem storing error handling information that is configured to direct the storage of error information in the shared memory subsystem in the BMC device. The operating system subsystem identifies a first error and generates first error information for the first error. The operating system subsystem then accesses the error handling information and, based on the error handling information, stores the first error information generated for the first error in the shared memory subsystem included in the BMC device. The operating system subsystem then notifies the BMC device of the first error information stored in the shared memory subsystem. The BMC device may then access the first error information in the shared memory subsystem and transmit the first error information to a computing device management system.

Abstract: A BIOS settings runtime modification authentication system includes a computing device having a user interface subsystem, a TPM device storing a platform owner authentication value, and a BIOS subsystem including BIOS settings. The BIOS subsystem generates a secret and creates challenge information with the TPM device using the secret. The challenge information is configured to allow the TPM device to retrieve the secret from the challenge information in response to the receiving the platform owner authentication value. During runtime operations for the computing device, the BIOS subsystem provides the challenge information via the user interface subsystem, receives a BIOS authentication request and the secret via the user interface subsystem and, in response, modifies at least one of the BIOS settings.

Abstract: An epoxy resin composition with epoxy groups and active hydrogens having different molar equivalents includes an epoxy resin component and a curing agent component. A mixing ratio of the epoxy resin component and the curing agent component is a mixing ratio of a cured product with the highest glass transition temperature Tg among cured products with different mixing ratios measured experimentally. According to a weight percentage in a total weight of the epoxy resin component, the epoxy resin component includes: 50 wt % to 100 wt % of a bisphenol A epoxy resin. According to a weight percentage in a total weight of the curing agent component, the curing agent component includes: 60 wt % to 98 wt % of polyetheramine (PEA) and 2 wt % to 20 wt % of a low-viscosity Mannich base.

Abstract: Three-dimensional (3D) semiconductor devices and fabricating methods are provided. In some implementations, a 3D semiconductor device includes: an array of vertical transistors each comprising a semiconductor body extending in a vertical direction; a plurality of word lines each extending in a first lateral direction, wherein each word line is shared by a row of the vertical transistors arranged along the first lateral direction; and a plurality of bit lines each extending in a second lateral direction perpendicular to the first lateral direction; wherein the semiconductor bodies are further arranged along a third lateral direction different from the first lateral direction and the second lateral direction.

Abstract: The present disclosure provides an array substrate, a display panel, and a method for manufacturing the array substrate, belonging to the field of display technologies. In the array substrate, a first electrode having a higher voltage in the first electrode and a second electrode of the transistor is disposed between an active layer and a base in a lower lap manner, and the second electrode having a lower voltage is disposed on a first insulating layer in an upper lap manner or disposed below the first insulating layer in the lower lap manner. When the second electrode is disposed in the upper lap manner, the problem that the transistor cannot operate normally due to the too large resistance at the second electrode can be avoided.

Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.

Abstract: A passivation film structure with passivation and surface doping includes a nano dielectric layer, a silicide layer and a hydrogen-rich dielectric layer sequentially laminated on a surface of a silicon substrate. The material of the nano dielectric layer is hydrogenated silicon oxide film or hydrogenated silicon oxynitride film; the material of the silicide layer is boron/phosphorus-doped hydrogenated carbon and/or nitrogen-containing silicon film; the material of the hydrogen-rich dielectric layer is selected from a laminated film of one or more of hydrogenated aluminum oxide film, hydrogenated silicon nitride film, hydrogenated silicon oxide film, and hydrogenated silicon oxynitride film. This structure has excellent passivation performance and can achieve good passivation effect on polished or textured silicon wafer or boron/phosphorus-diffused emitters. The passivation film structure contains boron/phosphorus element.

Abstract: An OOB component update system includes a computing device having BMC device coupled to a component. The BMC device receives a component update request that includes a component update image for updating the component, and a component update plugin. The BMC device then retrieves runtime parameter(s) for the computing device, and executes the component update plugin to determine whether the component update image is compatible with the runtime parameter(s). In response to the execution of the component update plugin determining that the component update image is not compatible with the runtime parameter(s), the BMC device prevents the updating of the component using the component update image. In response to the execution of the component update plugin determining that the component update image is compatible with the runtime parameter(s), the BMC device allows the updating of the component using the component update image.

Abstract: Examples of the present disclosure disclose a semiconductor device, a manufacturing method thereof and a memory device. The semiconductor device includes a plurality of bit lines and a conductive structure. The plurality of bit lines are located on a first side of a transistor and are arranged along a first direction. The conductive structure is located on a second side of the transistor and includes a first conductive portion and a second conductive portion. The first conductive portion is located between adjacent bit lines, and the second conductive portion is located on a side of the plurality of bit lines away from the transistor. The second conductive portion extends along the first direction and is connected to the first conductive portion between the adjacent bit lines.

Abstract: In various examples, a technique for generating speed change decisions for a mobile robot includes identifying, using one or more maps of a physical environment, one or more obstacles associated with one or more portions of a path of the mobile robot in the physical environment. The technique also includes generating, based at least on the one or more obstacles, one or more speed constraints, each speed constraint specifying a speed limit for a respective portion of the path. The technique further includes generating one or more speed change decisions specifying actions to be performed by the mobile robot to cause a speed profile of the mobile robot to satisfy the one or more speed constraints.

Abstract: The present disclosure provides a method for PCIE data transmission. The method includes: determining whether the length of a PCIE data packet to be transmitted is less than a preset length; when it is determined that the length of the PCIE data packet is less than the preset length, performing data transmission on the PCIE data packet by means of a space of a base address register and a protocol converter; and when it is determined that the length of the PCIE data packet is greater than or equal to the preset length, performing data reading/writing on the PCIE data packet in a DMA manner. Therefore, the utilization rate of a PCIE bandwidth is improved, and the running reliability of a host is improved.

Abstract: This disclosure relates to a highly integrated wireless ultrasonic motor (USM) system, comprising: a high-frequency inverter configured to convert DC power into high-frequency AC power; a first and second wireless power transfer channel connected to the inverter respectively, wherein the first wireless power transfer channel includes a first transmitting and receiving coils directly connected to a stator of the motor, and the second wireless power transfer channel includes a second transmitting and receiving coils directly connected to the stator, and wherein the stator resonates with the receiving coils when excited by a high-frequency magnetic field, generating a driving AC voltage; an autonomous optimal frequency adaptation control unit configured to detect zero-crossings of an inverter output current and to generate drive trigger commands to adjust a motor driving frequency; and a frequency-adaptive pulse step modulation (FAPSM) unit configured to dynamically adjust a pulse step amplitude and frequency of

Abstract: In certain aspects, a memory device includes an array of memory cells, and a plurality of peripheral circuits coupled to the array of memory cells and configured to control the array of memory cells. A first peripheral circuit of the plurality of peripheral circuits includes a first three-dimensional (3D) transistor. The first 3D transistor includes a 3D semiconductor body, and a gate structure in contact with a plurality of sides of the 3D semiconductor body. The gate structure includes a gate dielectric and a gate electrode. The gate electrode includes a metal. The gate dielectric has a thickness between 1.8 nm and 10 nm.

Abstract: Embodiments of this application provide a speaker module and an electronic device, and relate to the technical field of electronic devices. The electronic device includes an overall housing and at least one speaker. A sound outlet hole is provided on the overall housing. The speaker includes a speaker kernel, a front cavity, and a rear cavity, the front cavity has a sound outlet channel, and the sound outlet channel is in communication with the sound outlet hole. The speaker further includes an auxiliary cavity, and at least a part of the auxiliary cavity is located on a side of the front cavity facing away from the speaker kernel. The auxiliary cavity includes a transmission channel and a silencing cavity in communication with the transmission channel, the transmission channel is in communication with the front cavity through an auxiliary hole.

Abstract: A gate drive circuit for a half-bridge power module with a first and second GaN HEMT is disclosed. The circuit mitigates gate voltage overshoot, oscillation, and crosstalk induced by high dv/dt at the switching node. It includes a voltage clamp circuit, electrically connected to the gate of the first GaN HEMT, to suppress gate voltage overshoot. A negative voltage generation and control circuit is configured to generate and apply a negative voltage to the gate to offset positive crosstalk voltage spikes. A low-impedance Miller current path circuit is connected to the gate to provide a discharge path for Miller current, thereby suppressing negative crosstalk voltage spikes. The circuit provides robust protection for GaN HEMTs operating at high switching speeds.

Abstract: The present invention provides the use of tetramethylpyrazine nitrone derivatives in the treatment of ischemic stroke, including administration of a therapeutically effective amount of tetramethylpyrazine nitrone derivatives or pharmaceutical compositions thereof. In clinical experiments, it was unexpectedly found that the combination of TBN+t-PA significantly improved the NIHSS scores of neurological function in patients on the 30th and 90th days. In addition, the combination of TBN+t-PA significantly improved the neurological function mRS score of patients, and the complete cure rate (mRS score of 0) was significantly higher than that of the t-PA group.

Abstract: An array substrate sequentially includes a substrate, an active layer, a first metal layer, and a second passivation layer. The array substrate further includes a hydrogen barrier layer disposed between the active layer and the second passivation layer and covering at least a channel region, and a moisture discharge hole disposed to penetrate through at least the flat layer.

Abstract: Enhanced EPI techniques are described that acquire and record a second set of scan data with the same flyback trajectory as that used to acquire a first set of scan data, only with a shifted starting point. Doing so ensures that both Nyquist ghosting and flow ghosting can be improved without changing a necessary echo spacing. This also reducing imaging distortion and chemical shift, and without changing the bipolar readout gradient. A full set (according to Nyquist) of all k-space lines can be yielded for each polarity of the bipolar readout gradient.

Abstract: Disclosed are systems and techniques for wireless communications. For instance, a network entity may obtain a first plurality of bits from a first buffer, wherein a start position for obtaining the first plurality of bits from the first buffer is based on a redundancy version order. In some cases, the network entity may determine, based on a modulation order and a probability distribution associated with the first plurality of bits, at least one scaling factor for constellation mapping the first plurality of bits. In some examples, the network entity may map, based on the at least one scaling factor, the first plurality of bits to one or more symbols.

Abstract: Provided is a semiconductor power device. The semiconductor power device includes a semiconductor substrate and p-type body regions disposed in the semiconductor substrate. The p-type body regions are in contact with a source metal layer. The semiconductor substrate includes at least one first region, and a region of the semiconductor substrate outside the at least one first region is a second region. A p-type body region of p-type body regions in the first region is provided with a first p-type body region contact region, and the source metal layer is in contact with the first p-type body region contact region to form an ohmic contact. Each of p-type body regions in the second region forms no ohmic contact with the source metal layer.