Patents by Inventor Wei Liu

Wei Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240132395
    Abstract: Disclosed are a glass ceramic material, a preparation method thereof, and a denture. The glass ceramic material includes the following components by mass percentage: 58% to 72% of SiO2, 0% to 4% of Al2O3, 0% to 5% of Na2O, 3% to 8% of K2O, 8% to 17% of Li2O, 2.5% to 5% of P2O5, 0% to 2% of MgO, 0% to 2.5% of B2O3, 0% to 5% of ZnO and 0% to 3% of ZrO2. In the present application, by optimizing the composition and ratio of the glass ceramic material, and combining with a matching process system, it is possible to control the formation of lithium disilicate while the crystallinity of lithium metasilicate glass ceramic can be improved without an introduction of a high ratio of zirconia content, thereby improving the grinding performance of the glass ceramic. The present application is applicable to the field of material technology.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 25, 2024
    Applicant: SHENZHEN YURUCHENG DENTAL MATERIALS CO., LTD.
    Inventors: Zongyu LI, Wei LIU, Jian WANG, Jianjun LIU
  • Publication number: 20240132923
    Abstract: Provided is a recombinant microorganism including at least two genes for producing itaconic acid and its derived monomers, and the at least two genes are located on the same expression vector. The at least two genes include one encoding cis-aconitic acid decarboxylase and the other one encoding aconitase, and the genome of the recombinant microorganism includes a gene encoding the molecular chaperone protein GroELS. Also provided is a method for producing itaconic acid by using the microorganism.
    Type: Application
    Filed: March 22, 2023
    Publication date: April 25, 2024
    Inventors: I-Son NG, Jo-Shu CHANG, Chuan-Chieh HSIANG, Yeong-Chang CHEN, Yu-Chiao LIU, Chia-Wei TSAI
  • Publication number: 20240132925
    Abstract: The invention provides a method for preparing pyrrolidone, and the invention provides a method for catalytically preparing pyrrolidone with ?-aminobutyric acid in the presence of carnitine-CoA ligase CaiC. The carnitine-CoA ligase CaiC has an amino acid sequence as shown in SEQ ID NO:1. The ligase has catalytic activity in the cyclization of ?-aminobutyric acid to produce pyrrolidone. The carnitine-CoA ligase provided in the present invention affords a yield of pyrrolidone of 3.26 g/L and a molar yield of 39.53% in 24 h when ?-aminobutyric acid is used as a substrate, thus reducing the production period, improving the production of pyrrolidone, and accelerating the industrialization process of producing pyrrolidone by enzymatic conversion method.
    Type: Application
    Filed: October 18, 2022
    Publication date: April 25, 2024
    Inventors: Jing WU, Xuling JIANG, Liming LIU, Wei SONG, Yiwen ZHOU, Xiulai CHEN, LIU Jia, Cong GAO
  • Publication number: 20240136233
    Abstract: The present application provides a method for monitoring a gate oxide thickness: providing a device structure comprising a gate structure, a gate oxide layer under the gate structure, source and drain regions and a base region; applying a voltage ?Vdd on the gate structure so that an accumulation layer is formed between the source and drain regions, applying a small AC voltage on the basis of the gate voltage ?Vdd; grounding the source and drain regions; applying a voltage signal close to 0 potential on the base region; obtaining the capacitance Cox between the gate structure and the base region by testing; and obtaining the thickness of a gate oxide layer according to the formula Tox=?*S/Cox. This technique accurately monitors the thickness of the gate oxide layer, and avoids those errors caused by existing methods.
    Type: Application
    Filed: June 28, 2023
    Publication date: April 25, 2024
    Applicant: Shanghai Huali Integrated Circuit Corporation
    Inventors: Haibo LEI, Xingmei YANG, Shenlong XUAN, Wei LIU
  • Publication number: 20240134180
    Abstract: An optical device and the prism module thereof are provided. The prism module includes a first prism, a second prism, and a third prism. The second prism is disposed beside the first prism. The third prism is adhered to the second prism. First light enters the first prism, is reflected plural times in the first prism, enters the second prism, and is emitted from the second prism. Second light enters the second prism, is reflected plural times in the second prism, and is emitted from the second prism. Third light sequentially passes through the third prism and the second prism, enters the first prism, is reflected plural times in the first prism, and is emitted from the first prism.
    Type: Application
    Filed: October 19, 2023
    Publication date: April 25, 2024
    Inventors: Fei Han, Xiao-Yao Zhang, Yue-Ye Chen, Ling-Wei Zhao, Jun-Wei Che, Hua-Tang Liu
  • Publication number: 20240137221
    Abstract: Computer-implemented methods, non-transitory, computer-readable media, and computer-implemented systems implementing a one-touch login service are described. Information about a first IP address is obtained from a verification request sent by an application client device. A token is sent to the application client device. Information about a second IP address is obtained from a number acquisition request sent by an application server. Whether the first IP address is the same as the second IP address is determined. If the same, based on a token carried in the number acquisition request, a mobile phone number of a terminal device in which the application client device is located is obtained and the mobile phone number is sent to the application server. If not the same, sending the mobile phone number of the terminal device to the application server is refused.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Applicant: Alipay (Hangzhou) Information Technology Co., Ltd.
    Inventors: Wanqiao Zhang, Lin Huang, Juhu Nie, Yunding Jian, Wei Fu, Hongjian Cao, Yujia Liu
  • Patent number: 11965920
    Abstract: A method for achieving terminal-pair definition of four-terminal-pair (4TP) impedance and an application thereof are provided, which belongs to the field of precision measurement and metrology. A current output terminal of a two-stage follower is connected to a high current terminal of impedance through a coaxial line, and a voltage output terminal of the two-stage follower is connected to a high voltage terminal of the impedance through the coaxial line, which makes current of the high voltage terminal be 0, and core wire currents and outer wire currents of the high current terminal equal and reverse. The terminal-pair definition of the 4TP impedance can be satisfied; and the follower is added to make a bridge ratio variable and isolate effects of bridge load changes, thereby accelerating a balancing speed of the 4TP impedance bridge, and achieving accurate and fast comparative measurement having high precision of the 4TP AC impedance.
    Type: Grant
    Filed: November 6, 2023
    Date of Patent: April 23, 2024
    Assignee: NATIONAL INSTITUTE OF METROLOGY, CHINA
    Inventors: Yan Yang, Lu Huang, Dongxue Dai, Wei Wang, Xia Liu
  • Patent number: 11966241
    Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Huan-Neng Chen, Yen-Lin Liu, Chia-Wei Hsu, Jo-Yu Wu, Chang-Fen Hu, Shao-Yu Li, Bo-Ting Chen
  • Patent number: 11966546
    Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: April 23, 2024
    Assignee: E Ink Holdings Inc.
    Inventors: Chen-Cheng Lin, Chia-I Liu, Kun-Hsien Lee, Hung-Wei Tseng
  • Patent number: 11966711
    Abstract: Embodiments of the present disclosure relate to a solution for translation verification and correction. According to the solution, a neural network is trained to determine an association degree among a group of words in a source or target language. The neural network can be used for translation verification and correction. According to the solution, a group of words in a source language and translations of the group of words in a target language are obtained. An association degree among the group of words and an association degree among the translations can be determined by using the trained neural network. Then, whether there is a wrong translation can be determined based on the association degrees. In some embodiments, corresponding methods, systems and computer program products are provided.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: April 23, 2024
    Assignee: International Business Machines Corporation
    Inventors: Guang Ming Zhang, Xiaoyang Yang, Hong Wei Jia, Mo Chi Liu, Yun Wang
  • Patent number: 11966124
    Abstract: A display panel includes a display region and a photoelectric sensing region which includes a light transmitting region and a frame region surrounding the light transmitting region; the frame region includes a first region surrounding the light transmitting region, a second region on a side of the first region away from the light transmitting region and surrounding the first region, and a third region between the second region and the display region. The spacers are in an array and in the display region but not in the light transmitting region. A plurality of first support pillars are in the first region, arranged around the light transmitting region, and spaced from each other. A plurality of second support pillars are in the second region, around the second region, and spaced from each other. A plurality of third support pillars are in the third region in an array.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: April 23, 2024
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Kai Chen, Yanqing Chen, Ruichao Liu, Jie Tong, Xiaofeng Zhang, Weida Qin, Ning Wang, Yan Wang, Wei Li, Haoyi Xin
  • Publication number: 20240122921
    Abstract: The present invention relates to methods for treating patients with cancer, including patients with hematological malignancy, wherein the method comprises administering to the patient a therapeutically effective amount of a compound of formula (I), or a pharmaceutically acceptable salt thereof, wherein R1 and R2 are as defined herein.
    Type: Application
    Filed: September 25, 2023
    Publication date: April 18, 2024
    Inventors: Yifan ZHAI, Zi CHEN, Qian JIANG, Xiaojun HUANG, Wei LIU, Dajun YANG
  • Publication number: 20240128231
    Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are presented. In embodiments the methods of manufacturing include depositing a first bonding layer on a first substrate, wherein the first substrate comprises a semiconductor substrate and a metallization layer. The first bonding layer and the semiconductor substrate are patterned to form first openings. A second substrate is bonded to the first substrate. After the bonding the second substrate, the second substrate is patterned to form second openings, at least one of the second openings exposing at least one of the first openings. After the patterning the second substrate, a third substrate is bonded to the second substrate, and after the bonding the third substrate, the third substrate is patterned to form third openings, at least one of the third openings exposing at least one of the second openings.
    Type: Application
    Filed: January 4, 2023
    Publication date: April 18, 2024
    Inventors: Fu Wei Liu, Pei-Wei Lee, Yun-Chung Wu, Bo-Yu Chiu, Szu-Hsien Lee, Mirng-Ji Lii
  • Publication number: 20240128403
    Abstract: The present disclosure provides a micro light-emitting element, method for manufacturing a micro light-emitting element, and a light-emitting device. The micro light-emitting element includes a DBR structure layer, including a DBR adhesive layer, a DBR reflective layer, and a DBR sacrificial layer, where the DBR adhesive layer, the DBR reflective layer, and the DBR sacrificial layer are sequentially stacked. Subsequent structural coverage of a DBR reflective layer is improved by means of the DBR adhesion layer. Density of film layers of the DBR sacrificial layer, the DBR reflective layer, and the DBR adhesive layer are sequentially increased, so that etching rates of the DBR sacrificial layer, the DBR reflective layer, and the DBR adhesive layer are sequentially decreased during etching, thereby forming an inverted trapezoidal through hole which comprises an inclined side wall by an etching process.
    Type: Application
    Filed: December 22, 2023
    Publication date: April 18, 2024
    Applicant: XIAMEN CHANGELIGHT CO., LTD.
    Inventors: Wei LIU, Weiwen LIU, Shaowen PENG, Fengjie LIN, Hongyi ZHOU
  • Publication number: 20240126002
    Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 18, 2024
    Applicant: Coretronic Corporation
    Inventors: Chih-Jen Tsang, Chung-Wei Huang, Shih-Yen Cheng, Jung-Wei Chang, Han-Yuan Liu, Chun-Wei Lee
  • Publication number: 20240124852
    Abstract: The present application discloses a recombinant Newcastle disease virus genome, a recombinant Newcastle disease virus rNDV-VEGF-Trap containing the genome and a preparation method therefor, a DNA molecule encoding the recombinant Newcastle disease virus genome, and a use of the genome and the recombinant Newcastle disease virus in the preparation of a drug for treating cancer. The recombinant Newcastle disease virus provided by the present application relates to inserting a coding gene of VEGF-Trap into the genome of the recombinant Newcastle disease virus, such that the recombinant Newcastle disease virus obtained therefrom is replicated with a strong replication capability, thereby killing host cancer cells; moreover, the recombinant Newcastle disease virus has reliable safety for non-cancer cells, and shows improved anti-tumor effect and oncolytic efficiency.
    Type: Application
    Filed: April 13, 2022
    Publication date: April 18, 2024
    Inventors: Wei Xiao, Deshan Li, Tianyan Liu, Zhenzhong Wang, Yukai Cao, Zhihang Liu, Dan Yu
  • Publication number: 20240128142
    Abstract: The present application discloses a double-sided SiP packaging structure and a manufacturing method thereof, wherein the double-sided SiP packaging structure comprises a substrate, a first packaging structure arranged on the substrate, and a second packaging structure arranged below the substrate; the second packaging structure comprises a chip, interposer and a molding material; a conductive structure array is arranged on an upper surface of the interposer; the interposer is arranged below the substrate through the conductive structure array; a space region among a lower surface of the substrate, the chip and the interposer is filled with the molding material; a conductive bonding pad array is arranged on the lower surface of the interposer; and a groove is formed in a part of region between the conductive bonding pad and an edge contour of the interposer.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 18, 2024
    Applicant: JCET GROUP CO., LTD.
    Inventors: Shuo Liu, Yaojian Lin, Jianyong Wu, Wei Yan, Jing Zhao
  • Publication number: 20240126003
    Abstract: A light source module and a display device are provided. The light source module includes a light source, a light guide plate, and an optical film set including multiple first optical microstructures having a first surface, multiple second optical microstructures having a second surface, and multiple third optical microstructures having a third surface. Each of the multiple first optical microstructures has a first vertex angle, each of the multiple second optical microstructures has a second vertex angle, and each of the multiple third optical microstructures has a third vertex angle. The third vertex angle is less than the first vertex angle, and the first vertex angle is less than or equal to the second vertex angle. By configuring the aforementioned optical microstructures, the light source module of the disclosure may greatly improve the collimation of light and has favorable luminance.
    Type: Application
    Filed: October 16, 2023
    Publication date: April 18, 2024
    Applicant: Nano Precision Taiwan Limited
    Inventors: Hsin-Wei Chen, Wen-Yen Chiu, Chao-Hung Weng, Ming-Dah Liu
  • Publication number: 20240128313
    Abstract: A method includes providing a substrate, forming a patterned hard mask layer over the substrate, etching the patterned hard mask layer to form a hole that penetrates the patterned hard mask layer, forming a barrier portion in the hole, removing the patterned hard mask layer, and forming a gate structure over the substrate. Formation of the gate structure includes forming a dielectric body portion on the substrate. The barrier portion that is thicker than the dielectric body portion adjoins one end of the dielectric body portion. The dielectric body portion and the barrier portion are collectively referred to as a gate dielectric layer. Formation of the gate structure further includes forming a gate electrode on the gate dielectric layer and forming gate spacers on opposite sidewalls of the gate electrode. During formation of the gate spacers, a portion of the barrier portion is removed to form a recessed corner.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Tse-Hsiao LIU, Chih-Wei LIN, Po-Hao CHIU, Pi-Kuang CHUANG, Ching-Yi HSU
  • Publication number: 20240128120
    Abstract: A package structure and a manufacturing method thereof are disclosed. The structure includes at least one semiconductor die, a redistribution layer disposed on the at least one semiconductor die, and connectors there-between. The connectors are disposed between the at least one semiconductor die and the redistribution layer, and electrically connect the at least one semiconductor die and the redistribution layer. The redistribution layer includes a dielectric layer with an opening and a metallic pattern layer disposed on the dielectric layer, and the metallic pattern layer includes a metallic via located inside the opening with a dielectric spacer surrounding the metallic via and located between the metallic via and the opening.
    Type: Application
    Filed: March 30, 2023
    Publication date: April 18, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiang-Wei Liu, Chung-Kuang Lin