Patents by Inventor Wei-Lun Hsu

Wei-Lun Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152320
    Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: October 19, 2021
    Assignee: INPAQ TECHNOLOGY CO., LTD.
    Inventors: Yu-Ming Peng, Wei-Lun Hsu, Chu-Chun Hsu, Hong-Sheng Ke, Yu Chia Chang
  • Patent number: 11133394
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor strip over a substrate. The semiconductor strip includes a first semiconductor stack and a second semiconductor stack over the first semiconductor stack. A dummy gate stack is formed to cross the semiconductor strip. The dummy gate stack is replaced with a first metal gate stack and a second metal gate stack. The first metal gate stack is in contact with the first semiconductor layer of the first semiconductor stack and the second metal gate stack is in contact with the first semiconductor layer of the second semiconductor stack.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hao Wu, Zhi-Chang Lin, Ting-Hung Hsu, Kuan-Lun Cheng
  • Patent number: 11129239
    Abstract: The wireless communication device includes one or more wireless transceivers and a controller. The one or more wireless transceivers detect(s) one or more first frequency bands of one or more cellular networks, and detect(s) one or more second frequency bands of one or more non-cellular networks. The controller selects one of the first frequency bands and one of the second frequency bands, which do not overlap, and assigns the selected first frequency band to one of the wireless transceivers, thereby enabling one of the wireless transceivers to camp on a cell on the selected first frequency band. Also, the controller assigns the selected second frequency band to one of the wireless transceivers, thereby enabling one of the wireless transceivers to connect to one of the non-cellular networks on the selected second frequency band.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: September 21, 2021
    Assignee: MEDIATEK INC.
    Inventors: Wei-Lun Liu, Sheng-Kai Chang, I-Ching Hsieh, Yen-Chih Yang, Teng-Wei Huang, Tzu-Shiang Hsu, Tzu-Yu Lee, Tsung-Yueh Chiang
  • Patent number: 11119296
    Abstract: An imaging optical lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region. The second lens element with negative refractive power has an object-side surface being concave in a paraxial region. The third lens element has an object-side surface and an image-side surface being aspheric. The fourth lens element with negative refractive power has an object-side surface being concave and an image-side surface being concave in a paraxial region, wherein the image-side surface has convex shape in an off-axis region, and the two surfaces thereof are aspheric. The fifth lens element with positive refractive power has an object-side surface and an image-side surface being both aspheric.
    Type: Grant
    Filed: November 29, 2019
    Date of Patent: September 14, 2021
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Po-Lun Hsu, Wei-Yu Chen
  • Patent number: 11119550
    Abstract: A USB device and an operation method thereof are provided. The USB device includes a first switch, a second switch, a power converter, and a first USB connector. A first terminal of the first switch is configured to receive a first voltage. The power converter is configured to provide a second voltage, and the second voltage is less than the first voltage. A first terminal of the second switch is coupled to the power converter to receive the second voltage. A first power pin of the first USB connector is coupled to a second terminal of the first switch and a second terminal of the second switch.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: September 14, 2021
    Assignee: Aten International Co., Ltd.
    Inventors: Chun-Tang Tseng, Wei-Lun Hsu, Po-Wen Chen
  • Publication number: 20210118889
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.
    Type: Application
    Filed: December 25, 2020
    Publication date: April 22, 2021
    Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
  • Publication number: 20210109580
    Abstract: A USB device and an operation method thereof are provided. The USB device includes a first switch, a second switch, a power converter, and a first USB connector. A first terminal of the first switch is configured to receive a first voltage. The power converter is configured to provide a second voltage, and the second voltage is less than the first voltage. A first terminal of the second switch is coupled to the power converter to receive the second voltage. A first power pin of the first USB connector is coupled to a second terminal of the first switch and a second terminal of the second switch.
    Type: Application
    Filed: March 16, 2020
    Publication date: April 15, 2021
    Applicant: Aten International Co., Ltd.
    Inventors: Chun-Tang Tseng, Wei-Lun Hsu, Po-Wen Chen
  • Patent number: 10910386
    Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: February 2, 2021
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wei-Lun Hsu, Hung-Lin Shih, Che-Hung Huang, Ping-Cheng Hsu, Hsu-Yang Wang
  • Publication number: 20200381431
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Application
    Filed: August 18, 2020
    Publication date: December 3, 2020
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 10795255
    Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 6, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Wei-Lun Hsu, Gang-Yi Lin, Yu-Hsiang Hung, Ying-Chih Lin, Feng-Yi Chang, Ming-Te Wei, Shih-Fang Tzou, Fu-Che Lee, Chia-Liang Liao
  • Patent number: 10784261
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: September 22, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 10770464
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: September 8, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chien Liu, Chia-Lung Chang, Tzu-Chin Wu, Wei-Lun Hsu
  • Publication number: 20200123334
    Abstract: A method, i.e., trapping of structural coloration (TOSC), for fabricating solid 3D network-structured photonic crystals featuring tunable visible structural colorations includes the steps: a PS-PVP copolymer is dissolved in a chloride-containing solvent and is cast as an initial film, the copolymer self-assembles into 3D periodic network-structured morphology; the copolymer in the initial film is swollen in a polar solvent to form a solvated film; the solvated film is dried to form a solid photonic crystal. During evaporation of the polar solvent, the PVP blocks of the copolymer become glassy and form a thin glassy layer on the surface of the solvated film such that the 3D network structures of the copolymer in solvated state can be preserved into the solid photonic crystal revealing the similar periodicity and dimension to that in solvated state, which is very distinct from the film having 1D lamellar structure.
    Type: Application
    Filed: November 26, 2018
    Publication date: April 23, 2020
    Inventors: Yeo-Wan Chiang, En-Li Lin, Wei-Lun Hsu
  • Patent number: 10626234
    Abstract: A method, i.e., trapping of structural coloration (TOSC), for fabricating solid 3D network-structured photonic crystals featuring tunable visible structural colorations includes the steps: a PS-PVP copolymer is dissolved in a chloride-containing solvent and is cast as an initial film, the copolymer self-assembles into 3D periodic network-structured morphology; the copolymer in the initial film is swollen in a polar solvent to form a solvated film; the solvated film is dried to form a solid photonic crystal. During evaporation of the polar solvent, the PVP blocks of the copolymer become glassy and form a thin glassy layer on the surface of the solvated film such that the 3D network structures of the copolymer in solvated state can be preserved into the solid photonic crystal revealing the similar periodicity and dimension to that in solvated state, which is very distinct from the film having 1D lamellar structure.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: April 21, 2020
    Assignee: NATIONAL SUN YAT-SEN UNIVERSITY
    Inventors: Yeo-Wan Chiang, En-Li Lin, Wei-Lun Hsu
  • Publication number: 20200105764
    Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.
    Type: Application
    Filed: October 31, 2018
    Publication date: April 2, 2020
    Inventors: Wei-Lun Hsu, Gang-Yi Lin, Yu-Hsiang Hung, Ying-Chih Lin, Feng-Yi Chang, Ming-Te Wei, Shih-Fang Tzou, Fu-Che Lee, Chia-Liang Liao
  • Publication number: 20200098755
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Publication number: 20200035782
    Abstract: The present invention provides a semiconductor structure including a substrate including a plurality of capacitor lower electrodes, the capacitor lower electrodes are arranged in a diamond array along a first direction and a second direction respectively, the first direction and the second direction are not perpendicular to each other. A supporting structure layer contacts at least parts of the capacitor lower electrodes, wherein the supporting structure layer includes a plurality of triangular openings, and the three corners of each triangular opening are overlapped with three adjacent capacitor lower electrodes respectively.
    Type: Application
    Filed: August 29, 2018
    Publication date: January 30, 2020
    Inventors: Li-Wei Feng, En-Chiuan Liou, Yu-Cheng Tung, Wei-Lun Hsu, Yu-Hsiang Hung, Ming-Te Wei, Le-Tien Jung
  • Patent number: 10529715
    Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: January 7, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Yung-Chien Kung, Ming-Tsung Yeh, Yan-Hsiu Liu, Am-Tay Luy, Yao-Pi Hsu, Ji-Fu Kung
  • Patent number: 10475925
    Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.
    Type: Grant
    Filed: May 21, 2018
    Date of Patent: November 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Hsu, Hsin-Che Huang, Shyan-Liang Chou, Hung-Lin Shih
  • Patent number: 10419236
    Abstract: A method, system and non-transitory computer storage readable medium comprise operating a Wide Area Network (WAN) device according to a first Internet protocol (IP) translation mode of operation, changing an initial connectivity status between the WAN device and a WAN and transitioning from the first IP translation mode of operation to a second IP translation mode of operation that is different from the first IP translation mode of operation based on the change in the initial connectivity status.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: September 17, 2019
    Assignee: OPEN INVENTION NETWORK LLC
    Inventors: Wei-Lun Hsu, Pen Hsieh, Chia-Hung Fan, Chen-Hua Fan