Abstract: A photographing lens assembly includes, in order from an object side to an image side: a first, a second, a third, a fourth, a fifth and a sixth lens elements. The first lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, wherein the object-side surface has at least one convex critical point in an off-axis region thereof. The third lens element has an image-side surface being convex in a paraxial region thereof. The fourth lens element has positive refractive power. The fifth lens element with negative refractive power has an object-side surface being concave in a paraxial region thereof, and an image-side surface being convex in a paraxial region thereof. The sixth lens element has an image-side surface being concave in a paraxial region thereof, wherein the image-side surface has at least one convex critical point in an off-axis region thereof.

Abstract: The federated learning system includes a moderator and client devices. Each client device performs a method for verifying model update as follows: receiving a hash function and a general model; training a client model according to the general model and raw data; calculating a difference as an update parameter between the general model and the client model, sending the update parameter to the moderator; inputting the update parameter to the hash function to generate a hash value; sending the hash value to other client devices, and receiving other hash values; summing all the hash values to generate a trust value; receiving an aggregation parameter calculated according to the update parameters; inputting the aggregation parameter to the hash function to generate a to-be-verified value; and updating the client model according to the aggregation parameter when the to-be-verified value equals the trust value.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: An arrayed waveguide grating (AWG) can have a reusable delay line, a plurality of coupling devices, and a free propagation region (FPR). The delay line can have a continuous first waveguide connected to receive a plurality of wavelengths. Each coupling device can have a second waveguide coupled to a respective portion of the continuous first waveguide. The FPR can have input and output ends. The input end of the FPR can be coupled to receive the radiation from each of the coupling devices. The radiation can be directed to spatially-separated output channels based on wavelength at the output end of the FPR. The plurality of coupling devices and the delay line are configured to control power and phase distributions of the radiation transmitted to the FPR.

Abstract: A reconfigurable intelligent surface includes a radiant layer, a sensing feeding circuit layer, a processing layer and a controlling circuit layer. The radiant layer includes at least two antennas and a plurality of reflecting units. Each of the at least two antennas is configured for sensing a polarization, a frequency or a direction angle of an incident electromagnetic wave. The reflecting units are arranged to form a reflecting surface. The sensing feeding circuit layer is signally connected to the antennas. The processing layer is signally connected to the sensing feeding circuit layer, and the processing layer is configured to produce a controlling signal corresponding thereto. The controlling circuit layer is signally connected to the radiant layer and the processing layer, wherein the controlling circuit layer receives the controlling signal and controls the reflecting units according to the controlling signal to adjust and form a reflecting electromagnetic wave.

Abstract: A refrigeration cycle apparatus includes a refrigerant circuit and an adsorbent. The refrigerant circuit includes a compressor that compresses a refrigerant. The refrigerant circuit configures a vapor compression refrigeration cycle in which the refrigerant circulates. The adsorbent adsorbs and desorbs the refrigerant circulating in the refrigerant circuit. The adsorbent adsorbs and desorbs the refrigerant in accordance with a change in a pressure of the refrigerant circulating in the refrigerant circuit.

Abstract: A refrigerant circuit includes a compressor that compresses refrigerant and an expansion mechanism that decompresses refrigerant. The refrigerant circuit configures a vapor compression refrigeration cycle in which the refrigerant circulates. The adsorbent adsorbs and desorbs the refrigerant circulating in a first unit. The refrigerant circuit includes a high-pressure region and a low-pressure region. The refrigeration cycle apparatus is operated under at least one of a first condition and a second condition. In the first condition, the refrigerant in the high-pressure region has a pressure lower than or equal to a critical pressure of the refrigerant, and the refrigerant in the high-pressure region has a temperature exceeding a critical temperature of the refrigerant.

Abstract: The present invention discloses a meta-optics element comprising a substrate, a meta-optics structure and an anti-reflection structure. The meta-optics structure comprises multiple meta-optics units geometrically disposed on the substrate. The anti-reflection structure comprises multiple anti-reflection units corresponding to these meta-optics units and disposed on the surface of the corresponding meta-optics units. Besides, a manufacture method of meta-optics element is also disclosed.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.

Abstract: A pH-switchable carrier composition includes a plurality of bioactive glass particles, wherein each of the bioactive glass particle is optionally at least a partially coated with a surface modifier; wherein the bioactive glass particles, with or without, the surface modifier can bind to a nucleic acid compound upon contact at pH in the range of about 7 to about 11, and exhibit controlled release of the nucleic acid compound at pH in the range of about 5 to 6.

Abstract: An analyzing apparatus for molecules is provided. A pore device includes a cation selective nanopore, and a first chamber and a second chamber which are separated by the cation selective nanopore. In an initial state, the first chamber includes molecules to be analyzed, and the second chamber has higher salt concentration than the first chamber. A current sensor measures an ionic current flowing through a first electrode and a second electrode provided in the first chamber and the second chamber.

Abstract: A grid array type lead frame package includes a lead frame having a plurality of bonding fingers projecting inwardly from a periphery of the lead frame; a semiconductor device mounted on inner ends of the bonding fingers, wherein the semiconductor device comprises an active surface and a plurality of input/output (I/O) pads disposed on the active surface; a plurality of bonding wires extending between the I/O pads and the bonding fingers for transmitting signals from or to the semiconductor device; a molding compound at least partially encapsulating the semiconductor device, the bonding wires, and the bonding fingers; and a solder mask layer attached to a bottom surface of the molding compound and a bottom surface of each of the bonding fingers.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: The disclosure provides a semiconductor package structure, including a substrate having a front side and a back side, a first insulating layer disposed on the front side of the substrate, and a die disposed on the first insulating layer; wherein the die includes a first die pad and a second die pad, the first die pad coupled to a first portion of a metal layer, the second die pad coupled to a second portion of the metal layer, and the first portion of the metal layer and the second portion of the metal layer spaced apart by a second insulating layer. An associated semiconductor packaging method and another semiconductor package structure are also disclosed.

Abstract: A USB device and an operation method thereof are provided. The USB device includes a first switch, a second switch, a power converter, and a first USB connector. A first terminal of the first switch is configured to receive a first voltage. The power converter is configured to provide a second voltage, and the second voltage is less than the first voltage. A first terminal of the second switch is coupled to the power converter to receive the second voltage. A first power pin of the first USB connector is coupled to a second terminal of the first switch and a second terminal of the second switch.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; forming a conductive layer in the trench; forming a metal layer on the conductive layer; forming a mask layer on the metal layer; and patterning the mask layer, the metal layer, and the conductive layer to form a bit line structure.

Abstract: A USB device and an operation method thereof are provided. The USB device includes a first switch, a second switch, a power converter, and a first USB connector. A first terminal of the first switch is configured to receive a first voltage. The power converter is configured to provide a second voltage, and the second voltage is less than the first voltage. A first terminal of the second switch is coupled to the power converter to receive the second voltage. A first power pin of the first USB connector is coupled to a second terminal of the first switch and a second terminal of the second switch.

Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.