Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

Abstract: A method, i.e., trapping of structural coloration (TOSC), for fabricating solid 3D network-structured photonic crystals featuring tunable visible structural colorations includes the steps: a PS-PVP copolymer is dissolved in a chloride-containing solvent and is cast as an initial film, the copolymer self-assembles into 3D periodic network-structured morphology; the copolymer in the initial film is swollen in a polar solvent to form a solvated film; the solvated film is dried to form a solid photonic crystal. During evaporation of the polar solvent, the PVP blocks of the copolymer become glassy and form a thin glassy layer on the surface of the solvated film such that the 3D network structures of the copolymer in solvated state can be preserved into the solid photonic crystal revealing the similar periodicity and dimension to that in solvated state, which is very distinct from the film having 1D lamellar structure.

Abstract: A method, i.e., trapping of structural coloration (TOSC), for fabricating solid 3D network-structured photonic crystals featuring tunable visible structural colorations includes the steps: a PS-PVP copolymer is dissolved in a chloride-containing solvent and is cast as an initial film, the copolymer self-assembles into 3D periodic network-structured morphology; the copolymer in the initial film is swollen in a polar solvent to form a solvated film; the solvated film is dried to form a solid photonic crystal. During evaporation of the polar solvent, the PVP blocks of the copolymer become glassy and form a thin glassy layer on the surface of the solvated film such that the 3D network structures of the copolymer in solvated state can be preserved into the solid photonic crystal revealing the similar periodicity and dimension to that in solvated state, which is very distinct from the film having 1D lamellar structure.

Abstract: A method of forming a layout definition of a semiconductor device includes the following steps. Firstly, a plurality of first patterns is established to form a material layer over a substrate, with the first patterns being regularly arranged in a plurality of columns along a first direction to form an array arrangement. Next, a plurality of second patterns is established to surround the first patterns. Then, a third pattern is established to form a blocking layer on the material layer, with the third pattern being overlapped with a portion of the second patterns and with at least one of the second patterns being partially exposed from the third pattern. Finally, the first patterns are used to form a plurality of first openings in a stacked structure on the substrate to expose a portion of the substrate respectively.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: The present invention provides a semiconductor structure including a substrate including a plurality of capacitor lower electrodes, the capacitor lower electrodes are arranged in a diamond array along a first direction and a second direction respectively, the first direction and the second direction are not perpendicular to each other. A supporting structure layer contacts at least parts of the capacitor lower electrodes, wherein the supporting structure layer includes a plurality of triangular openings, and the three corners of each triangular opening are overlapped with three adjacent capacitor lower electrodes respectively.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.

Abstract: A method, system and non-transitory computer storage readable medium comprise operating a Wide Area Network (WAN) device according to a first Internet protocol (IP) translation mode of operation, changing an initial connectivity status between the WAN device and a WAN and transitioning from the first IP translation mode of operation to a second IP translation mode of operation that is different from the first IP translation mode of operation based on the change in the initial connectivity status.

Abstract: According to an embodiment of the present invention, a method for fabricating semiconductor device includes the steps of: forming a semiconductor layer on a substrate; removing part of the semiconductor layer and part of the substrate to form a trench; forming a liner in the trench; removing part of the liner to form a spacer adjacent to two sides of the trench; and forming a bit line structure in the trench.

Abstract: A method for fabricating semiconductor device includes the steps of: forming a bit line structure on a substrate; forming a first spacer, a second spacer, and a third spacer around the bit line structure; forming an interlayer dielectric (ILD) layer on the bit line structure; planarizing part of the ILD layer; removing the ILD layer and the second spacer to form a recess between the first spacer and the third spacer; and forming a liner in the recess.

Abstract: An anti-roll bar device with a variable rigidity has a first arm assembly having multiple first joining units, a second arm assembly having multiple second joining units, and a variable rigidity unit mounted between the first arm assembly and the second arm assembly and having multiple abutment portions and a variable rigidity coefficient. The first and second joining units are staggered with each other annularly and abut the abutment portions. When a vehicle passes a bumpy terrain, a slight force is exerted on the variable rigidity unit and is absorbed by the variable rigidity unit, such that the vehicle can be kept from tilting and shaking up and down. When the vehicle is in cornering, a larger force is exerted on the variable rigidity unit to increase a rigidity of the variable rigidity unit, such that the variable rigidity unit can transfer torques to keep the vehicle from tilting.

Abstract: A method for forming a complementary metal oxide semiconductor device is disclosed. First, a substrate having a first device region and a second device region is provided. A first trench is formed in the first device region and filled with a first material. A second trench is formed in the second device region and filled with a second material. The first material and the second material comprise different stresses. After that, a first gate structure and a second gate structure are formed on the first material and the second material and completely covering the first trench and the second trench, respectively.

Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.

Abstract: A method of forming a semiconductor device includes following steps. First of all, plural mandrel patterns are formed on a target layer. Then, plural capping layers are formed to cover a top region and sidewalls of each of the mandrel patterns, respectively. Next, plural spacers are formed at two sides of each of the capping layers, respectively. Following these, a portion of the spacers and the capping layers covered on the top regions of the mandrel patterns are simultaneously removed, and the capping layers is then removed completely.

Abstract: An integrated circuit (IC) structure includes a substrate having several regions, several semiconductor devices formed at the substrate and respectively within the regions, and an ultra-deep (UD) trench isolation structure formed in the substrate. The substrate has a top surface and a bottom surface oppositely, and the UD trench isolation structure formed in the substrate surrounds peripheries of each of the regions for structurally and physically isolating the semiconductor devices within different regions. The UD trench isolation structure penetrates the substrate by extending from the top surface of the substrate to the bottom surface of the substrate.

Abstract: A complementary metal oxide semiconductor (CMOS) device is disclosed. The CMOS device includes a substrate with a first device region and a second device region formed thereon. A first isolation structure is formed in the first device region, and includes a first trench filled with a first material. A second isolation structure is formed in the second device region and includes a second trench filled with a second material. The first material and the second material have different stresses. A first gate structure is disposed atop the first material and completely covering the first trench. A second gate structure is disposed atop the second material and completely covering the second trench.

Abstract: A method, system and non-transitory computer storage readable medium comprise operating a Wide Area Network (WAN) device according to a first Internet protocol (IP) translation mode of operation, changing an initial connectivity status between the WAN device and a WAN and transitioning from the first IP translation mode of operation to a second IP translation mode of operation that is different from the first IP translation mode of operation based on the change in the initial connectivity status.