Patents by Inventor Wei Min

Wei Min has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250110395
    Abstract: A heat dissipation module includes an airflow generator, a heat dissipation substrate connected to a heat source, a heat dissipation member, a baffle, and a heat conductive member connected to the heat dissipation substrate. The heat dissipation member includes a main body and first fins arranged around an outer periphery of the main body and forming an accommodation space with the main body. The airflow generator has a rotation axis, and is accommodated in the accommodation space and connected to the main body. The baffle is connected to the first fins and has an opening corresponded to an air inlet surface of the airflow generator. On a reference plane perpendicular to the rotation axis, at least a part of an orthographic projection of each first fin does not overlap an orthographic projection of the airflow generator, and an orthographic projection of the baffle overlaps the orthographic projections of the first fins.
    Type: Application
    Filed: September 24, 2024
    Publication date: April 3, 2025
    Applicant: Coretronic Corporation
    Inventors: Wei-Min Chien, Tung-Chou Hu, Yao-Hung Chen
  • Patent number: 12267489
    Abstract: A coding algorithm encodes consecutive frames of a video sequence and realizes distributed Gradual Decoding Refresh. The consecutive frames include a first frame, a second frame, and a third frame, and each frame is composed of (X+Y+Z) columns of coding tree units. The algorithm includes: coding X columns of the first frame in an intra coding manner and coding the other columns of the first frame in an inter coding manner and/or the intra coding manner; coding X columns of the second frame in the inter coding manner, coding Y columns of the second frame in the intra coding manner, and coding Z columns of the second frame in the inter and/or intra coding manner(s); and coding X and Y columns of the third frame in the inter coding manner, and coding Z columns of the third frame in the intra coding manner. The X/Y/Z columns (intra-coded columns) are inconsecutive.
    Type: Grant
    Filed: December 6, 2022
    Date of Patent: April 1, 2025
    Assignee: REALTEK SEMICONDUCTOR CORP.
    Inventors: Wei-Min Zeng, Chi-Wang Chai, Wu-Jun Chen, Wei Li, Rong Zhang
  • Publication number: 20250107077
    Abstract: A semiconductor device includes a substrate, a plurality of memory arrays and a plurality of capacitors. The substrate includes a plurality of memory array regions. Each memory array region includes a plurality of memory blocks and a plurality of dummy blocks. The dummy blocks are located along a boundary of the memory blocks. The plurality of memory arrays are disposed in the plurality of memory blocks. The plurality of capacitors are disposed in the plurality of dummy blocks along the boundary of the plurality of memory blocks. The plurality of memory arrays may include 3D NAND flash memories with high capacity and high performance.
    Type: Application
    Filed: September 27, 2023
    Publication date: March 27, 2025
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Wei Min Chen, Wei Chun Tseng, Lan Ting Huang
  • Publication number: 20250092913
    Abstract: An upper dustproof member of a linear guideway includes a connection segment and two floating dustproof segments that are respectively connected to two opposite sides of the connection segment. Each of the two floating dustproofing segments has a carrying bar and at least one rib that is connected to the carrying bar. In each of the two floating dustproofing segments, the carrying bar has two end portions each having a bevel arranged away from the at least one rib. When the bevels of the end portions of the upper dustproof member are respectively inserted into four tolerance slots of two end caps, each of the end portions and the corresponding end cap have a tolerance gap therebetween, so that a slanting surface of each of the bevels abuts against the corresponding tolerance slot, and each of the end portions is deformable toward the corresponding tolerance gap.
    Type: Application
    Filed: January 8, 2024
    Publication date: March 20, 2025
    Inventors: JO-HSUAN CHANG, WEI-MIN WANG, YUE-RU SUNG, JHIH-JIE LUO
  • Patent number: 12255255
    Abstract: A device includes a first fin and a second fin extending from a substrate, the first fin including a first recess and the second fin including a second recess, an isolation region surrounding the first fin and surrounding the second fin, a gate stack over the first fin and the second fin, and a source/drain region in the first recess and in the second recess, the source/drain region adjacent the gate stack, wherein the source/drain region includes a bottom surface extending from the first fin to the second fin, wherein a first portion of the bottom surface that is below a first height above the isolation region has a first slope, and wherein a second portion of the bottom surface that is above the first height has a second slope that is greater than the first slope.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Min Liu, Li-Li Su, Yee-Chia Yeo
  • Patent number: 12252448
    Abstract: In the present disclosure, an engineered stone is provided. The engineered stone includes a first full-body stone pattern, a second full-body stone pattern and a printed stone pattern. The first full-body stone pattern includes a first stone formulation. The second full-body stone pattern includes a second stone formulation, and the second stone formulation is different from the first stone formulation, wherein the first full-body stone pattern and the second full-body stone pattern are located on a front surface, a plurality of side surfaces and a back surface opposite to the front surface of the engineered stone. The printed stone pattern is located on the front surface of the engineered stone, and the printed stone pattern is overlapped with the first full-body stone pattern and the second full-body stone pattern.
    Type: Grant
    Filed: February 22, 2024
    Date of Patent: March 18, 2025
    Assignee: QUEEN CERAMIC INCORPORATION
    Inventors: Cheng-Hsuan Lai, Wei-Min Chen, Lei Lin
  • Publication number: 20250085583
    Abstract: Provided is a display panel, including: a base substrate, a display structure, a black matrix pattern, and a cylindrical lens structure layer. The black matrix pattern includes a plurality of first openings. The display panel is provided with a plurality of sub-pixel regions arranged in rows and columns. The first openings are disposed in the sub-pixel regions. The cylindrical lens structure layer includes a plurality of strip-shaped cylindrical lens structure and has a plurality of focal lines in an orthographic projection on the black matrix pattern. The focal lines are parallel to the length direction of the cylindrical lens structures. The focal lines partition each sub-pixel region into a plurality of regions. One of the plurality of regions is a non-crosstalk region. The black matrix pattern further includes second openings in the non-crosstalk regions. The second openings are disposed outside regions where the first openings are disposed.
    Type: Application
    Filed: August 19, 2022
    Publication date: March 13, 2025
    Inventors: Shiming SHANG, Xiaoqing PENG, Hailin XUE, Weida QIN, Yanyun LI, Shaokai SU, Shaoming YAN, Wei MIN
  • Publication number: 20250076664
    Abstract: A head-mounted display, which includes a case body, a heat source, and a thermally conductive material layer. The heat source and the thermally conductive material layer are disposed in the case body. The heat source is connected to the case body through the thermally conductive material layer. The case body has a first surface connected to the thermally conductive material layer and an opposite second surface. The thermally conductive material layer has a third surface connected to the heat source and an opposite fourth surface. A first distance is greater than a second distance, in which the first distance is a distance from the third surface adjacent to the heat source toward the second surface, and the second distance is a distance from the third surface away from the heat source toward the second surface. In this way, the internal heat of the head-mounted display can be uniformly distributed.
    Type: Application
    Filed: February 6, 2024
    Publication date: March 6, 2025
    Applicant: Coretronic Corporation
    Inventors: Yao-Hung Chen, Wei-Min Chien
  • Patent number: 12245412
    Abstract: A device includes first and second gate electrodes, a word line and a first metal island. The first gate electrode corresponds to transistors of a memory cell. The second gate electrode is separated from the first gate electrode and corresponds to the transistors. The word line is coupled to the memory cell and located between the first and the second gate electrodes. The first metal island is configured to couple a first power supply to the memory cell. A first boundary of the first metal island is located between first and second boundaries of the first gate electrode and is located between first and second boundaries of the word line, and each of the first boundary of the first gate electrode and the first boundary of the word line is located between first and second boundaries of the first metal island.
    Type: Grant
    Filed: July 31, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hidehiro Fujiwara, Wei-Min Chan, Chih-Yu Lin, Yen-Huei Chen, Hung-Jen Liao
  • Patent number: 12241384
    Abstract: A rotor blade system. The rotor blade system includes a rotor and a plurality of blades coupled to the rotor. The plurality of blades are arranged in an airfoil distribution pattern. The airfoil distribution pattern includes one or more baseline blades and one or more intentionally mistuned blades including an intentional mistuning feature.
    Type: Grant
    Filed: April 4, 2024
    Date of Patent: March 4, 2025
    Assignee: GENERAL ELECTRIC COMPANY
    Inventors: Wei-Min Ren, Letian Wang, Kevin E. Turner, Yoon Seok Choi
  • Patent number: 12243931
    Abstract: The present disclosure is directed to methods for forming source/drain (S/D) epitaxial structures with a hexagonal shape. The method includes forming a fin structure that includes a first portion and a second portion proximate to the first portion, forming a gate structure on the first portion of the fin structure, and recessing the second portion of the fin structure. The method further includes growing a S/D epitaxial structure on the recessed second portion of the fin structure, where growing the S/D epitaxial structure includes exposing the recessed second portion of the fin structure to a precursor and one or more reactant gases to form a portion of the S/D epitaxial structure. Growing the S/D epitaxial structure further includes exposing the portion of the S/D structure to an etching chemistry and exposing the portion of the S/D epitaxial structure to a hydrogen treatment to enhance growth of the S/D epitaxial structure.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Min Liu, Yee-Chia Yeo, Li-Li Su
  • Patent number: 12235570
    Abstract: The disclosure provides a projection apparatus, which includes a casing, a projection module, at least one airflow generating unit, and at least one speaker. The casing has at least one air outlet. The projection module is disposed in the casing and configured to project an image beam outside the casing. The airflow generating unit is disposed in the casing and configured to generate airflow. The speaker is disposed in the casing, and the airflow generating unit is located between the projection module and the speaker. The speaker has at least one flow guiding surface, and the flow guiding surface is inclined toward the air outlet to guide the airflow toward the air outlet. The projection apparatus has a favorable heat dissipation capability and may reduce the noise generated by the airflow generating unit.
    Type: Grant
    Filed: June 20, 2022
    Date of Patent: February 25, 2025
    Assignee: Coretronic Corporation
    Inventors: Yi-Cheng Hou, Wei-Min Chien, Tung-Chou Hu
  • Publication number: 20250060602
    Abstract: A wearable projection device includes a body, an optical engine module, a heat-dissipation component, and a control module. The body has an air inlet, and a containing space connected to the air inlet. The optical engine module is disposed in the containing space. The heat-dissipation component disposed in the containing space is configured to dissipate heat from the optical engine module. The heat-dissipation component includes a vapor chamber and an airflow generator. The vapor chamber is connected to the optical engine module. The airflow generator is positioned on the vapor chamber, and the airflow generator includes a piezoelectric thin film. The control module is disposed on the body, electrically connected to the optical engine module and the airflow generator, and configured to drive the piezoelectric thin film to vibrate, so that an external cooling airflow enters the containing space through the air inlet to cool the vapor chamber.
    Type: Application
    Filed: July 21, 2024
    Publication date: February 20, 2025
    Applicant: Coretronic Corporation
    Inventors: Yao-Hung Chen, Wei-Min Chien
  • Publication number: 20250046367
    Abstract: A memory circuit includes an array including a plurality of memory cells arranged across a plurality of columns and a plurality of voltage control circuits, each of the plurality of voltage control circuits operatively coupled to the memory cells of a corresponding one of the plurality of columns. Each of the plurality of voltage control circuits includes a first portion configured to provide a first voltage drop in coupling a supply voltage to the memory cells of the corresponding column and a second portion configured to provide a second voltage drop in coupling the supply voltage to the memory cells of the corresponding column. The first voltage drop is substantially smaller than the second voltage drop.
    Type: Application
    Filed: February 20, 2024
    Publication date: February 6, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kao-Cheng Lin, Yen-Huei Chen, Wei Min Chan, Hidehiro Fujiwara, Wei-Cheng Wu, Pei-Yuan Li, Chien-Chen Lin, Shang Lin Wu
  • Publication number: 20250024671
    Abstract: A memory device is provided which includes a first memory cell including a first transistor and a second transistor coupled to the first transistor in parallel. Gates of the first transistor and the second transistor are coupled to each other, and the gates of the first transistor and the second transistor pass different layers and overlap with each other. Types of the first transistor and the second transistor are the same.
    Type: Application
    Filed: July 11, 2023
    Publication date: January 16, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien Hui Huang, Kao-Cheng LIN, Wei Min CHAN, Shang Lin WU, Chia-Chi HUNG, Wei-Cheng WU, Chia-Che CHUNG, Pei-Yuan LI, Chien-Chen LIN, Yung-Ning TU, Yen Lin CHUNG
  • Publication number: 20250002976
    Abstract: A method for optical super-multiplexing using polyynes to provide enhanced images from stimulated Raman microscopy is disclosed. In some exemplary embodiments, the polyynes are organelle-targeted or spectral barcoded. Imaging can be enhanced by using the polyynes to image whole live cells or specific organelles within live cells. The polyynes can also be used in optical data storage (i.e., encoding) and identification (i.e., decoding) applications.
    Type: Application
    Filed: July 10, 2024
    Publication date: January 2, 2025
    Inventors: Wei MIN, Fanghao HU
  • Publication number: 20250006815
    Abstract: A method includes forming a first bottom-tier transistor; forming a second bottom-tier transistor, the first and second bottom-tier transistors sharing a same source/drain region; forming a first top-tier transistor over the first bottom-tier transistor, the first top-tier transistor comprising a first channel layer and a first gate structure around the first channel layer; forming a second top-tier transistor over the second bottom-tier transistor, the second top-tier transistor comprising a second channel layer and a second gate structure around the second channel layer, the first and second top-tier transistors sharing a same source/drain region, wherein from a top view, a first dimension of the first channel layer in a lengthwise direction of the first gate structure is different than a second dimension of the second channel layer in the lengthwise direction of the first gate structure.
    Type: Application
    Filed: June 27, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kao-Cheng LIN, Cheng-Yin WANG, Yen Lin CHUNG, Wei Min CHAN, Yen-Huei CHEN
  • Publication number: 20250005255
    Abstract: A system includes a processor for performing a thermal analysis for an IC layout, which includes a redistribution structure having a plurality of conductive layers stacked one upon another in a thickness direction. In response to a property of a first conductive layer satisfying a first condition, the processor applies a first modeling rule to the first conductive layer to obtain a first model, and, in response to the property of a second conductive layer satisfying a second condition but not the first condition, the processor applies a second modeling rule different from the first modeling rule to the second conductive layer to obtain a second model. The processor performs a thermal simulation for the IC layout based on the first and second models, and, based on the thermal simulation result, modifies the IC layout or proceeds with manufacturing one or more IC devices corresponding to the IC layout.
    Type: Application
    Filed: October 31, 2023
    Publication date: January 2, 2025
    Inventors: Kai Fai CHANG, Johnny Chiahao LI, Wei-Min TSENG, Chun-Hsien WEN, Jerry Chang Jui KAO, Chih-Wei CHANG
  • Patent number: 12176574
    Abstract: A porous carrier including a cellulose substrate and a functional layer is provided. The functional layer is located on at least one surface of the cellulose substrate, wherein the functional layer includes an organic polymer elastic filler and a polymer binder. An electrochemical device separator including the porous carrier is also provided.
    Type: Grant
    Filed: May 21, 2020
    Date of Patent: December 24, 2024
    Assignee: Taiwan Hopax Chemicals Mfg. Co., Ltd.
    Inventors: Hideya Yoshitake, Wei-Min Chang, Li-Jane Her, Tsung-Tien Kuo, Kai-Chi Chang
  • Patent number: RE50258
    Abstract: A projection device includes a light source module, an optical engine module, a projection lens, a housing, and at least one first heat dissipating element. The housing comprises a first end and a second end opposite to each other. The at least one first heat dissipating element is disposed in the housing, and each of the at least one first heat dissipating element includes a first plate portion, a second plate portion, and a first fin portion. The first plate portion is connected to the light source module. The second plate portion is connected to the first plate portion. The first fin portion is connected to the second plate portion and includes a plurality of first fins arranged at intervals. These first fins are arranged between the first end and the second end.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: December 31, 2024
    Assignee: Coretronic Corporation
    Inventors: Jhih-Hao Chen, Wei-Min Chien, Tsung-Ching Lin, Shi-Wen Lin