Abstract: A porous carrier including a cellulose substrate and a functional layer is provided. The functional layer is located on at least one surface of the cellulose substrate, wherein the functional layer includes an organic polymer elastic filler and a polymer binder. An electrochemical device separator including the porous carrier is also provided.

Abstract: An IC device includes a first and second stacked transistor structures including respective first and second and third and fourth transistors in a semiconductor substrate, first and second bit lines and a word line on one of a front or back side of the semiconductor substrate, and a power supply line on the other of the front or back side. The first transistor includes a source/drain (S/D) terminal electrically connected to the first bit line, a S/D terminal electrically connected to a S/D terminal of the second transistor, and a gate electrically connected to the word line, the third transistor includes a S/D terminal electrically connected to the second bit line, a S/D terminal electrically connected to a S/D terminal of the fourth transistor, and a gate electrically connected to the word line, and the second and fourth transistors include S/D terminals electrically connected to the power supply line.

Abstract: A method of operating a memory device is provided. A clock signal is received. Each clock cycle of the clock signal initiates a write operation or a read operation in a memory device. A power nap period is then determined. The power nap period is compared with a clock cycle period to determine that the power nap period is less than the clock cycle period of the clock signal. A header control signal is generated in response to determining that the power nap period is less than the clock cycle period. The header control signal turns off a header of a component of the memory device.

Abstract: In an embodiment, a device includes: a first nanostructure; a source/drain region adjoining a first channel region of the first nanostructure, the source/drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source/drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.

Abstract: An embodiment includes a device including a first fin extending from a substrate. The device also includes a first gate stack over and along sidewalls of the first fin. The device also includes a first gate spacer disposed along a sidewall of the first gate stack. The device also includes a first source/drain region in the first fin and adjacent the first gate spacer, the first source/drain region including a first carbon-containing buffer layer on the first fin. The device also includes and a first epitaxial structure on the first carbon-containing buffer layer.

Abstract: A memory device is provided. The memory device comprises a memory cell, a first power rail and a suppressing circuit. The memory cell is coupled to a word line. The first power rail transmits a first supply voltage. The suppressing circuit comprises a first transistor and a second transistor. The first transistor is diode-connected, coupled to the word line, and disposed at a first layer. The second transistor is diode-connected coupled between the first transistor and the first power rail, and disposed at a second layer under the first layer. The first transistor and the second transistor overlap with each other in a layout view.

Abstract: A device includes a first nanostructure over a semiconductor substrate; a second nanostructure over the first nanostructure; a gate structure surrounding the first nanostructure and the second nanostructure; a first epitaxial region in the semiconductor substrate adjacent the gate structure, wherein the first epitaxial region is a first doped semiconductor material; and a second epitaxial region over the first epitaxial region, wherein the second epitaxial region is adjacent the first nanostructure and the second nanostructure, wherein the second epitaxial region is a second doped semiconductor material that is different from the first doped semiconductor material. In an embodiment, the first doped semiconductor material has a smaller doping concentration than the second doped semiconductor material.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

Abstract: A semiconductor device includes a first transistor cell. The first transistor cell generates a first current signal and a second current signal indicating a bit of a physical unclonable function. The first transistor cell includes a first transistor, a second transistor and a third transistor. The first transistor outputs the first current signal. The second transistor generates the first current signal from a first source/drain structure of the second transistor, and generates the second current signal from a second source/drain structure of the second transistor. The third transistor outputs the second current signal. The first transistor, the second transistor and the third transistor are stacked in order along a first direction. The first source/drain structure of the second transistor and the second source/drain structure of the second transistor are arranged along a second direction different from the first direction.

Abstract: Exemplary computer-accessible medium, systems, and methods are described herein which can provide an excited fluorescence radiation. In accordance with certain exemplary embodiments of the present disclosure, an excited fluorescence radiation can be provided using a beam of a probe so as to excite a molecule to an excited state for a fluorescence emission to effectuate the excited fluorescence radiation. The molecule can be detected based on the fluorescence emission. For example, the beam of the probe can be either the near-infrared spectrum or the visible light spectrum.

Abstract: A method includes flowing first precursors over a semiconductor substrate to form an epitaxial region, the epitaxial region includes a first element and a second element; converting a second precursor into first radicals and first ions; separating the first radicals from the first ions; and flowing the first radicals over the epitaxial region to remove at least some of the second element from the epitaxial region.

Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

Abstract: Whether a voltage difference reaches a hysteresis voltage of a hysteresis comparator is used to efficiently update a charge of a capacitor and achieve lower power consumption. On the other hand, since the advanced voltage holding circuit is designed to consume lower power, the refresh time must be designed longer, which makes it impossible to do a large number of yield tests. Thus, the test time in conjunction with the relevant application circuit can be greatly shortened, and the testability and reliability of a voltage holding device can be increased.

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices are described herein. The method includes steps for patterning fins in a multilayer stack and forming an opening in a fin as an initial step in forming a source/drain region. The opening is formed into a parasitic channel region of the fin. Once the opening has been formed, a first semiconductor material is epitaxially grown at the bottom of the opening to a level over the top of the parasitic channel region. A second semiconductor material is epitaxially grown from the top of the first semiconductor material to fill and/or overfill the opening. The second semiconductor material is differently doped from the first semiconductor material. A stack of nanostructures is formed by removing sacrificial layers of the multilayer stack, the second semiconductor material being electrically coupled to the nanostructures.

Abstract: An object recognition method includes generating Doppler spectrogram data according to an echo signal, the echo signal being relating to an object; transforming N sets of time-domain data of the Doppler spectrogram data corresponding to N velocities into N sets of cadence spectrogram data, respectively; combining the N sets of spectrogram data to obtain 1D/2D cadence spectrum data, and acquiring a series of cadence feature from the 1D/2D cadence spectrum data to recognize the object.

Abstract: An on-chip or built-in self-test (BIST) module for an RFIC is provided. The BIST module can be implemented in an RFIC system, which may include a beamforming module of a radar system. The BIST module may include components and methods to up-convert a signal from a test frequency to RF at an input to the RFIC and down-convert and output signal.

Abstract: A memory cell includes a first and second transmission pass-gate, a read word line and a write word line. The first transmission pass-gate includes a first and second pass-gate transistor. The second transmission pass-gate includes a third and fourth pass-gate transistor. The read word line is on a first metal layer above a front-side of a substrate. The write word line is on a second metal layer below a back-side of the substrate opposite from the front-side of the substrate. The first pass-gate transistor and the third pass-gate transistor are turned on in response to the write word line signal during a write operation. The second pass-gate transistor and the fourth pass-gate transistor are turned on in response to the read word line signal during the write operation after the first pass-gate transistor and the third pass-gate transistor are turned on.

Abstract: Disclosed herein are related to memory device including an adaptive word line control circuit. In one aspect, the memory device includes a memory cell and a word line driver coupled to the memory cell through a word line. In one aspect, the memory device includes an adaptive word line control circuit including two or more diodes connected in series, where one of the two or more diodes is coupled to the word line.

Abstract: A variable gain amplifier is disclosed having parallel sets of transistors and control for bias voltages, wherein the average of bias voltage values is strategically controlled to reduce phase variance. For example, a variable gain amplifier may include a first set of transistors coupled to a first bias voltage, a second set of transistors coupled to a second bias voltage, where the second set of transistors is coupled in parallel with the first set of transistors, and a control module adapted to control the first and second bias voltages, the control module adapted to reduce the gain of the first set of transistors while increasing the gain of the second set of transistors.