Abstract: A semiconductor device and method of manufacturing the semiconductor device are provided. An exemplary semiconductor device comprises a fin disposed over a substrate, wherein the fin includes a channel region and a source/drain region; a gate structure disposed over the substrate and over the channel region of the fin; a source/drain feature epitaxially grown in the source/drain region of the fin, wherein the source/drain feature includes a top epitaxial layer and a lower epitaxial layer formed below the top epitaxial layer, and the lower epitaxial layer includes a wavy top surface; and a contact having a wavy bottom surface matingly engaged with the wavy top surface of the lower epitaxial layer of the source/drain feature.

Abstract: Various examples of an integrated circuit with a sidewall spacer and a technique for forming an integrated circuit with such a spacer are disclosed herein. In some examples, the method includes receiving a workpiece that includes a substrate and a gate stack disposed upon the substrate. A spacer is formed on a side surface of the gate stack that includes a spacer layer with a low-k dielectric material. A source/drain region is formed in the substrate; and a source/drain contact is formed coupled to the source/drain region such that the spacer layer of the spacer is disposed between the source/drain contact and the gate stack.

Abstract: The present disclosure provides low resistance contacts and damascene interconnects with one or more graphene layers in fin structures of FETs. An example semiconductor device can include a substrate with a fin structure that includes an epitaxial region. The semiconductor device can also include an etch stop layer on the epitaxial region, and an interlayer dielectric layer on the etch stop layer. The semiconductor device can further include a metal contact, above the epitaxial region, formed through the etch stop layer and the interlayer dielectric layer, and a graphene film at interfaces between the metal contact and each of the epitaxial region, the etch stop layer, and the interlayer dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure extended above a substrate along a first direction, and a first gate structure formed over the first fin structure along a second direction. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first fin structure and adjacent to the first gate structure, and a cap layer formed on and in direct contact with the first S/D structure. The semiconductor device structure includes an isolation structure adjacent to the first gate structure and the first S/D structure along the first direction. The isolation structure extends from the first gate structure to the first S/D structure, and the first S/D structure has a protruding portion toward to the isolation structure, and the protruding portion of the first S/D structure is separated from the isolation structure by the cap layer.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

Abstract: A sheet input module includes: a tray; a support plate pivotally disposed on the tray to form a first included angle with the tray, wherein the support plate supports multiple sheets; and a sheet-stopper structure being pivotally disposed on the tray and providing a stopping function for the sheets. In an interlocking mode, the sheet-stopper structure is driven by the support plate according to a change of the first included angle and rotated relatively to the tray to adjust a second included angle between a stopping surface of the sheet-stopper structure and the sheets. A printing device using the sheet input module is also provided.

Abstract: A pressure generating device includes a tank, a deformable membrane, a driving device, and an actuating arm. The tank defines a chamber therein, and includes an opening and a communication port each of which is in fluid communication with the chamber. The deformable membrane is disposed to seal the opening, and is deformable between a flat state and a deformed state. The actuating arm is coupled to be driven by the driving device to move between a first position, where the deformable membrane is in the flat state, and a second position, where the deformable membrane is forced to be in the deformed state, such that a predetermined negative pressure is generated through the communication port when the actuating arm is driven from one of the first and second positions to the other one of the first and second positions.

Abstract: A power factor high-voltage end synchronous rectifier includes a bridge rectifying module, a power factor module and a high-voltage synchronous rectifier, whereby the high-voltage synchronous rectifier obtains the state of a second power outputted by the bridge rectifying module through a current detector and generates first and second control signals. The first control signal adjusts the on/off state of a first wide bandgap compound semiconductor of the power factor module, and the second control signal adjusts the on/off state of a second wide bandgap compound semiconductor of the power factor module, allowing the high-voltage synchronous rectifier to generate a plurality of control signals at the same time, so that the second power of the power module can be switched between continuous conduction mode (CCM), discontinuous conduction mode (DCM) and quasi resonant mode (QR) in a very short time (can be regarded as zero second in an ideal state).

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: A burner of a gas stove includes a burner body, a partition member, and at least one flame cover. The burner body includes a gas conduit and a base. The gas conduit has at least one gas input passage for injecting gas and air, and the base has at least one mixture passage for mixing the gas and the air. The at least one mixture passage communicates with the at least one gas input passage. The partition member has a plurality of through holes and covers the at least one mixture passage. The at least one flame cover provided with a plurality of flame holes covers the partition member. Whereby, the size of the burner of the gas stove is reduced significantly, and the gas can mix with the air effectively and uniformly.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure extended above a substrate along a first direction, and a first gate structure formed over the first fin structure along a second direction. The semiconductor device structure includes a first source/drain (S/D) structure formed over the first fin structure and adjacent to the first gate structure, and a cap layer formed on and in direct contact with the first S/D structure. The semiconductor device structure includes an isolation structure formed adjacent to the first gate structure and the first S/D structure along the first direction, and a bottom surface of the isolation structure is lower than a bottom surface of the first gate structure and a bottom surface of the first S/D structure.

Abstract: A video conferencing system including a plurality of ultra-wideband (UWB)-enabled electronic devices and a camera can facilitate a better conference call experience for participants. Each electronic device can determine its relative location by performing a UWB exchange with the camera. A conference call application uses the relative locations of each electronic device to generate an ordered listing of conference participants. The electronic devices adjust a graphical user interface (GUI) of conference participants based on the ordered listing. When one of the electronic devices detects an audio input from a corresponding conference participant, the electronic device can selectively provide audio information to the conference call application and request that the camera zoom to the electronic device. The camera can accordingly zoom a video input of the conference call application to emphasize the corresponding participant in the conference call.

Abstract: The disclosure relates to methods for determining an endometrial status using a sample, for example, an endometrial biopsy, from a woman, comprising: (a) performing an assay on the endometrial sample from the woman to determine a microRNA (miRNA) expression profile of the endometrial sample, wherein the miRNA expression profile comprises expression levels of a plurality of miRNAs, for example, 167 miRNAs having the sequences of SEQ ID NOs:1-167, respectively; and (b) analyzing the miRNA expression profile to obtain a receptivity predictive score using, for example, a computer-based algorithm. Aspects of the disclosure further relate to kits suitable for performing the methods, as well as uses of the kits for diagnostic and therapeutic purposes.

Abstract: A position calibration system and method are disclosed, in which a control unit is provided to control a positioner sensing module to scan a circular positioner provided on a positioning substrate in a first direction and a second direction so as to acquire midpoints of two scanned line segments and acquire an intersection of lines extending from the two center points in a direction perpendicular to the first and the second directions as a calibration reference point, which correspond to a centroid (a center) of the circular positioner. The calibration reference point functions as a reference point for positioning the positioning substrate with respect to the positioner sensing module and is stored in a memory unit. The calibration reference point can be used as a positioning point during installation of a machine and can also be used for calibration of a position of the machine.

Abstract: A display apparatus includes a wireless transmission unit and a display panel. The display panel includes a substrate, a plurality of pixel units and a signal line. The substrate includes a display region and a periphery region. The periphery region surrounds the display region. The pixel units are disposed on the display region. Each of the pixel units includes an active device and a pixel electrode. The active device is electrically connected to the pixel electrode. The signal line is on the periphery region. As viewed from a top view, the signal line has an annular shape having a gap and surrounds the display region.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.