Abstract: Some implementations described herein provide techniques and apparatuses for determining a performance of a dry-clean operation within a deposition tool. A cleaning-control subsystem of the deposition tool may include a gas concentration sensor and a temperature sensor mounted in an exhaust system of the deposition tool to monitor the dry-clean operation. The gas concentration sensor may provide data related to a concentration of a chemical compound in a cleaning gas, where the chemical compound is a bi-product of the dry-clean operation. The temperature sensor may provide temperature data related to an exothermic reaction of the dry-clean operation. Such data may be used to determine an efficiency and/or an effectiveness of the dry-clean operation within the deposition tool.

Abstract: Techniques described herein enable respective (different) types of metal silicide layers to be formed for p-type source/drain regions and n-type source/drain regions in a selective manner. For example, a p-type metal silicide layer may be selectively formed over a p-type source/drain region (e.g., such that the p-type metal silicide layer is not formed over the n-type source/drain region) and an n-type metal silicide layer may be formed over the n-type source/drain region (which may be selective or non-selective). This provides a low Schottky barrier height between the p-type metal silicide layer and the p-type source/drain region, as well as a low Schottky barrier height between the n-type metal silicide layer and the n-type source/drain region. This reduces the contact resistance for both p-type source/drain regions and n-type source/drain regions.

Abstract: A system including computer readable storage media including executable instructions and one or more processors configured to execute the executable instructions to obtain a schematic netlist and a performance specification for an integrated circuit, determine electrical constraints for nets in the schematic netlist based on the performance specification, determine physical constraints from the electrical constraints, rout the nets in the schematic netlist based on the electrical constraints and the physical constraints, and provide a data file of a layout.

Abstract: A semiconductor memory device and method of making the same are disclosed. The semiconductor memory device includes a substrate that includes a memory region and a peripheral region, a transistor including a metal gate located in the peripheral region, a composite dielectric film structure located over the metal gate of the transistor, the composite dielectric film structure including a first dielectric layer and a second dielectric layer over the first dielectric layer, where the second dielectric layer has a greater density than a density of the first dielectric layer, and at least one memory cell located in the memory region. The composite dielectric film structure provides enhanced protection of the metal gate against etching damage and thereby improves device performance.

Abstract: A method for CMP includes following operations. A first metal layer and a second metal layer are formed in a dielectric structure. The second metal layer is formed over a portion of the first metal layer. A first composition is provided to remove a portion of the first metal layer. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed to expose the second metal layer. A CMP operation is performed to remove a portion of the first metal layer, a portion of the second metal layer and a portion of the dielectric structure.

Abstract: An optimized pulse shaping clock data recovery system is provided that includes a slicer configured to receive a signal and provide an initial set of tentative decisions to a decision feedforward equalizer, where the decision feedforward equalizer provides a fully equalized output signal. The slicer may be incorporated as part of decision feedback equalizer to provide better quality tentative decisions. The clock data recovery system also receives the first output signal that is partially equalized in such a way as to optimally shape it for a clock to sample it at an ideal location by providing an adjustment signal to the analog to digital controller.

Abstract: The invention provides an optical coherence tomography self-testing system, an optical coherence tomography method and an ocular disease monitoring system. The optical coherence tomography self-testing system comprises a camera device, an external display module and a communication module. The camera device includes an image-capturing module and a processing module. The image-capturing module captures a plurality of ocular images. The processing module is connected to the image-capturing module, and the processing module determines whether a position offset value between the pupil center position of a tested eyeball and an optical axis of the image-capturing module is within a preset error range. If the position offset value is within the preset error range, the plurality of ocular images is stored as a plurality of displayed images. The external display module displays one of the plurality of displayed images and a status light after the image-capturing module has completed image capturing.

Abstract: A semiconductor device including a gaseous spacer and a method for forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a substrate; forming a first gate spacer on sidewalls of the gate stack; forming a second gate spacer over the first gate spacer; removing a portion of the second gate spacer, at least a portion of the second gate spacer remaining; removing the first gate spacer to form a first opening; and after removing the first gate spacer, removing the remaining portion of the second gate spacer through the first opening.

Abstract: A method of fabricating a fin-like field effect transistor (FinFET) device includes providing a semiconductor substrate having a region for forming p-type metal-oxide-semiconductor (PMOS) devices and a region for forming n-type metal-oxide-semiconductor (PMOS) devices, forming fin structures in both regions of the substrate separated by isolation features, first forming source/drain (S/D) features in the PMOS region, and subsequently forming S/D features in the NMOS region. First forming the PMOS S/D features and then forming the NMOS S/D features results in a greater extent of loss of isolation features in the PMOS region than in the NMOS region.

Abstract: A semiconductor device includes a substrate; an isolation structure over the substrate; a fin over the substrate and the isolation structure; a gate structure engaging a first portion of the fin; first sidewall spacers over sidewalls of the gate structure and over a second portion of the fin; source/drain (S/D) features adjacent to the first sidewall spacers; and second sidewall spacers over the isolation structure and over sidewalls of a portion of the S/D features. The second sidewall spacers include silicon oxide, silicon nitride, or silicon oxynitride. The second sidewall spacers and the second portion of the fin include a same dopant, wherein the dopant includes phosphorus.

Abstract: A differential channel circuit structure is disclosed. The differential channel circuit structure comprises a first differential circuit including a differential channel and a termination circuit. The differential channel has a differential mode impedance and a common mode impedance, and includes a first end and a second end, each capable of processing at least a first differential signal and a first common mode signal. The termination circuit includes a third end and a fourth end connected to the first end and the second end of the differential channel respectively, so as to simultaneously match the differential mode impedance and the common mode impedance of the differential channel.

Abstract: A low thermal budget dielectric material treatment is provided. An example method of the present disclosure includes providing a semiconductor structure, depositing a dielectric material over the semiconductor structure, treating the dielectric material with a gaseous species carried in a supercritical fluid, and after the treating, reducing a thickness of the dielectric material.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a substrate, at least two gate structures disposed over the substrate, each of the at least two gate structures including a gate electrode and a spacer disposed along sidewalls of the gate electrode, wherein the spacer includes a refill portion and a bottom portion, the refill portion of the spacer has a funnel shape such that a top surface of the refill portion of the spacer is larger than a bottom surface of the refill portion of the spacer, and a source/drain contact disposed over the substrate and between the spacers of the at least two gate structures.

Abstract: A semiconductor device according to the present disclosure includes a gate-all-around (GAA) transistor in a first device area and a fin-type field effect transistor (FinFET) in a second device area. The GAA transistor includes a plurality of vertically stacked channel members and a first gate structure over and around the plurality of vertically stacked channel members. The FinFET includes a fin-shaped channel member and a second gate structure over the fin-shaped channel member. The fin-shaped channel member includes semiconductor layers interleaved by sacrificial layers.

Abstract: In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: A radio frequency (RF) front-end circuit of a wireless communication device is provided. The RF front-end circuit includes a receiving amplifier, a down-converter, an up-converter, a transmitting amplifier and an output driver, where the receiving amplifier and the down-converter are configured to process received signals according to a local oscillation (LO) signal, and the up-converter, the transmitting amplifier and the output driver are configured to process transmitted signals according to the LO signal. The receiving amplifier, the up-converter or the transmitting amplifier includes a transformer load. The transformer load includes a switchable inductor. When the wireless communication device operates in a first mode, the LO signal has a first frequency, and the switchable inductor has a first inductance. When the wireless communication device operates in a second mode, the LO signal has a second frequency, and the switchable inductor has a second inductance.

Abstract: An electronic package structure includes first and second package modules combined with each other. The first package module includes a substrate and a first electronic component disposed thereon, at least one second electronic component, and an insulation film. The first electronic component and the second electronic component are adjacent to each other. The insulation film includes a base material and a foam glue body, and the foam glue body is viscous and compressible. The second package module includes a heat dissipation plate and a liquid metal and an insulation protrusion portion disposed thereon. The liquid metal is pressed by the heat dissipation plate and the first electronic component. The insulation protrusion portion covers and abuts against the insulation film to press the foam glue body through the base material so as to deform the foam glue body and enable the foam glue body to cover the second electronic component.

Abstract: The present disclosure generally relates to systems and methods for evaluating viability of oocytes. In some implementation examples, an image sequence associated with an oocyte being aspirated into a pressure tool is obtained. Based on the image sequence and pressures applied on the oocyte, morphological features and mechanical features associated with the oocyte can be derived. At least some of the features can then be fed into a machine learning model to determine metrics indicative of quality of the oocyte, where a particular metric may be indicative of blastocyst formation. Optionally, the determined oocyte quality information can be presented to a user via an interactive user interface.

Abstract: The present disclosure provides a method and a non-transitory computer-readable medium for arranging components within a semiconductor device. The method includes providing a plurality of electrical components in a pre-layout, generating a first layout by routing the plurality of electrical components, obtaining a first resistance between a power terminal of the first layout and a first terminal of a first electrical component in the first layout, comparing the first resistance and a first threshold, adjusting routing of the first layout such that the first resistance is less than the first threshold, and generating a tape out file for the semiconductor device according to the first layout.