Abstract: A semiconductor package structure is disclosed. The semiconductor package structure includes: a substrate having a front surface and a back surface; a chip-on-interposer structure mounted on the front surface of the substrate; a back side stiffener mounted over the back surface of the substrate and surrounding a projection of the chip-on-interposer structure from a back surface perspective; and a plurality of conductive bumps mounted on the back surface of the substrate.

Abstract: Formation methods of a chip package are provided. The method includes bonding a first chip structure and a second chip structure over a substrate. The method also includes forming a release film to cover top surfaces of the first chip structure and the second chip structure. The method further includes forming a package layer to surround the first chip structure and the second chip structure after the formation of the release film. In addition, the method includes removing the release film such that the top surface of the first chip structure, the top surface of the second chip structure, and a top surface of the package layer are exposed.

Abstract: The present invention provides herbal compositions comprise Radix Dioscoreae, Radix Codonopsis, and Radix Astragalus Membranaceus. The herbal compositions are used to suppress intestinal glucose uptake of intestinal villus and decrease blood glucose levels. The present invention also provides methods of regulating blood glucose levels by administrating the herbal compositions.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the first chip structure and the second chip structure are different. The chip package also includes a package layer covering sidewalls of the first chip structure and sidewalls of the second chip structure. Top surfaces of the first chip structure and the second chip structure are not covered by the package layer.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: An electronic device comprises a central processing unit, a central processing unit governor, a graphics processing unit, a graphics processing unit governor and a governing framework. The governing framework comprises a user demand classifier, a unified policy selector, and a frequency-scaling intent communicator. An electronic device energy saving method is provided to bridge the processor-level gap and demand-level gap in order to reduce energy consumption of graphics-intensive applications.

Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

Abstract: A method includes performing a first light-exposure and a second a second light-exposure on a photo resist. The first light-exposure is performed using a first lithograph mask, which covers a first portion of the photo resist. The first portion of the photo resist has a first strip portion exposed in the first light-exposure. The second light-exposure is performed using a second lithograph mask, which covers a second portion of the photo resist. The second portion of the photo resist has a second strip portion exposed in the second light-exposure. The first strip portion and the second strip portion have an overlapping portion that is double exposed. The method further includes developing the photo resist to remove the first strip portion and the second strip portion, etching a dielectric layer underlying the photo resist to form a trench, and filling the trench with a conductive feature.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form an electrical interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: A media editing device obtains a digital image, and a facial region of an individual in the digital image is identified by a facial region analyzer. A plurality of facial features of the facial region is identified by a facial feature identifier. A skin color of the facial region is determined, and eyebrow regions in the facial region are identified based on the facial features. Each of the eyebrow regions is partitioned into a plurality of segments, and a determination is made, for one or more of the segments, whether an area above or an area below the segment has a color matching the skin color. The segment is designated as a verified eyebrow region or as an overlapped region depending on whether the area above or the area below the segment has a color matching the skin color. A special effect is applied on the verified eyebrow region.

Abstract: A LED lighting system efficiently provides an operating voltage powering integrated circuits. A LED string has LEDs segregated into LED groups connected in series. A LED controller has channel nodes connected to the cathodes of the LED groups respectively, and an output node connected to a capacitor providing the operating voltage. The LED controller drains a channel current from a selected channel node among the channel node. The LED controller regulates the channel current to a channel target value corresponding to the selected channel node, and provides a portion of the channel current as a charging current to power and regulate the operating voltage.

Abstract: An integrated circuit is suitable for use in an AC LED lamp and is configured to control a power bank coupled between a rectified input voltage and a ground voltage. The AC LED lamp has LED groups arranged in series between the rectified input voltage and the ground voltage. The power bank has a capacitor storing electric energy and a discharge switch coupled between the capacitor and the rectified input voltage. The integrated circuit has a path controller and a bank controller. The path controller controls conduction paths, each coupling a corresponding LED group to the group voltage. The bank controller turns on the discharge switch in response to a first path signal corresponding to a first conduction path, and turns off the discharge switch in response to a second path signal corresponding to a second conduction path. The first and second path signals are different from each other.

Abstract: A LED lighting system efficiently provides an operating voltage powering integrated circuits. A LED string has LEDs segregated into LED groups connected in series. A LED controller has channel nodes connected to the cathodes of the LED groups respectively, and an output node connected to a capacitor providing the operating voltage. The LED controller drains a channel current from a selected channel node among the channel node. The LED controller regulates the channel current to a channel target value corresponding to the selected channel node, and provides a portion of the channel current as a charging current to power and regulate the operating voltage.

Abstract: A semiconductor device, and a method of forming the device, are provided. The semiconductor device includes a first die having a first plurality of contact pads and a second die having a second plurality of contact pads. A substrate is bonded to a first contact pad of the first plurality of contact pads and a first contact pad of the second plurality of contact pads in a face-to-face orientation with the first die and the second die. A first through via extends through the substrate. Molding material is interposed between the first die, the second die and the substrate, the molding material extending along sidewalls of the first die, the second die, and the substrate. A second through via is positioned over a second contact pad of the first plurality of contact pads, the second through via extending through the molding material.

Abstract: A nucleotide sequence having SEQ ID NO:1, a universal reverse primer having SEQ ID NO:2, a universal RT primer, a method for designing primer, and a miRNA detection method are provided. In the miRNA detection method, the universal RT primer is used for the cDNA synthesis of a miRNA sample and the universal reverse primer is used for cDNA molecule amplification in qPCR quantitative detection. The universal reverse primer sequence, the nucleotide sequence, and the design rules are used in the method for designing primer, so as to design a primer for qPCR quantitative detection.

Abstract: An artificial retinal prosthesis system comprises an extraocular optical device and an intraocular retina chip. The extraocular optical device receives an external image, converts it into an optical pulse signal, and generates light energy. The intraocular retina chip receives the optical pulse signal from the extraocular optical device and produces an electric simulation signal. The intraocular retina chip includes a solar cell module receiving and converting the light energy into electric energy as a power source of the intraocular retina chip. The artificial retinal prosthesis system uses an optical modulation method to convert an image signal into an optical pulse signal, transmits the optical pulse signal into the eyeball, and decodes the optical pulse signal intraocularly. Thereby, the signal light intensity is improved without affect the contrast ratio.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a first chip structure and a second chip structure. Heights of the first chip structure and the second chip structure are different. The chip package also includes a package layer covering sidewalls of the first chip structure and sidewalls of the second chip structure. Top surfaces of the first chip structure and the second chip structure are not covered by the package layer.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip.

Abstract: A method for reducing noise is used to divide a received voice into plural voice segments and set a predetermined energy value. The energy of voice segment which is higher than the predetermined energy value is determined as normal voice and outputs directly, and the energy of voice segment which is lower than the predetermined energy value is determined as noise and will be processed.