Abstract: A wave power generation system comprises a heavy plate; an expansion pipe installed on a top of the heavy plate; a motion module installing on a top of the expansion pipe; a buoy installing on a top of the motion module, a top end of the motion module through the buoy and the top end connected to the buoy; and a motion control module having a base installing in the heavy plate; a driving unit installed in the base; and multiple blades coupled to the driving unit.

Abstract: A wave power generation system includes a power generation component and a hydraulic component. The hydraulic component includes a cylinder and a piston. The cylinder connects to the power generation component. The cylinder has an accommodation space and a vent located in the middle section of the accommodation space such that the vent runs outside from the accommodation space. The accommodation space is used for accommodating a fluid. The piston is disposed in the accommodation space and is used for being guided by the accommodation space and sliding relative to the cylinder. Thereby, this drives the power generation component to convert mechanical energy into electrical energy, and to force the remaining air in the accommodation space and remaining air in the fluid to be discharged via the vent.

Abstract: A resource allocation method adapted to a mobile device having a multi-core central processing unit (CPU) is provided. The CPU executes at least one application. The method includes steps as follows. A usage status of each of the at least one application is obtained according to a level of concern of a user for each of the at least one application. A sensitivity of at least one thread of each of the at least one application is determined according to the usage status of each of the at least one application. Resources of the CPU are allocated according to the sensitivity of the at least one thread run by the cores.

Abstract: An input module is mounted on a portable electronic device and has a sensing substrate and a cover lens mounted on a top surface of the sensing substrate, a physical switch mounted on and electrically connected to a bottom surface of the sensing substrate, and a flexible bridging board having two opposite short sides respectively protruding from two short sides of the sensing substrate for the two short sides of the flexible bridging board to be mounted on the electronic device. As the two short sides of the input module are mounted on the electronic device and a lever arm between a pressed point to a fixed point of the input module is shortened, a torque applied to the input module is lowered and the input module is not easily deformed.

Abstract: Disclosed herein is a method for preparing a near infrared shielding fiber. The method includes the steps of preparing and compounding a composition, then pelletizing the compounded composition to obtain the near-infrared shielding masterbatch, and melt spinning the near-infrared shielding masterbatch into the near-infrared shielding fiber. The composition includes at least one metallic ionic compound powder in an amount of about 1-25 wt %, a cross-linking agent in an amount of about 0.1-2 wt %, a thermoplastic polymer in an amount of about 67-98.7 wt %, a cross-linking initiator in an amount of about 0.1-1 wt %, and a dispersing agent in an amount of about 0.1-2 wt %.

Abstract: A three-dimensional chip stack includes a first chip bonded to a second chip to form a bonded interconnection therebetween. The bonded interconnection includes a first conductive pillar overlying a first substrate of the first chip, a second conductive pillar overlying a second substrate of the second chip, and a joint structure between the first conductive pillar and the second conductive pillar. The joint structure includes a first IMC region adjacent to the first conductive pillar, a second IMC region adjacent to the second conductive pillar, and a metallization layer between the first IMC region and the second IMC region.

Abstract: A system and method are provided to edit interactive three-dimensional multimedia. A user interface of the system is provided with an event level template that includes event series levels with multiple event developing points. Through the user interface, multiple interactive events related to a first character of the event developing point are edited. Through a three-dimensional engine, interactive relevances are built up between interactive events and multiple materials inside one or more database. When the interactive three-dimensional multimedia with multiple materials is output, the interactive events corresponding to the event developing points are performed according to a user command. An online editing and exchanging method integrated with the system and method is also provided to share pre-edited templates on an exchange server; each of the pre-edited templates is extracted from an interactive three-dimensional multimedia pre-edited by the system and method.

Abstract: LED controllers, LED lighting systems and control methods capable of providing an average luminance intensity independent from the variation of an AC voltage. A string of LEDs are divided into LED groups electrically connected in series between a power source and a ground. A LED controller has path switches, each for coupling a corresponding LED group to the ground. A management center controls the path switches, for making an input current from the power source to the string substantially approach a target value. A line waveform sensor coupled to the power source holds a representative signal during a cycle time of the power source. The representative signal is in response to an attribute of the power source, and substantially determines the target value.

Abstract: A solar cell includes a solar cell body, a plurality of busbars and a plurality of finger electrodes. The number of the finger electrodes is adjusted according to a width of the finger electrodes, a gap between the finger electrodes and a laid length of the solar cell body, such that a photovoltaic conversion efficiency of the solar cell can be substantially enhanced.

Abstract: A solar cell is disclosed, which includes: a semiconductor substrate, an anti-reflective layer, a passivation layer, a back electrode and back bus bar. The semiconductor substrate has a first surface and a second surface. The anti-reflective layer is disposed on the first surface. The back electrode is a continuous electrode or a flat electrode overlapping the whole back side of the solar cell. The continuous electrode or the flat electrode connects to the semiconductor substrate through a continuous opening. In another embodiment, the continuous electrode is passing through the passivation layer directly and connecting to the semiconductor substrate. That is, the solar cell includes a continuous opening or a continuous electrode.

Abstract: A solar cell includes a photovoltaic substrate having a first surface and a second surface and a plurality of bus bar electrode net structures. The bus bar electrode net structures are separately disposed on the first surface, each bus bar electrode net structure includes a bus bar electrode, a plurality of finger electrodes, at least one connecting line electrode and at least one vertical finger electrode. The bus bar electrode is disposed on the first surface. The finger electrodes are separately disposed at two sides of the bus bar electrode. The connecting line electrode is disposed on the first surface. Each connecting line electrode connects with ends of at least two finger electrodes. The vertical finger electrode is disposed on the first surface, and is parallel to the bus bar electrode and disposed between the two ends of the finger electrode to connect with at least two adjacent finger electrodes.

Abstract: A first dielectric layer is formed over a substrate. A second dielectric layer is formed over the first dielectric layer. A first opening is formed in the second dielectric layer. A second opening is formed in the first dielectric layer.

Abstract: A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

Abstract: A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

Abstract: A solar cell with doping blocks is provided, which includes: a semiconductor substrate, an anti-reflection layer, a plurality of front electrodes, and a back electrode layer. The semiconductor substrate has a first surface, and a plurality of doping block layers is arranged under the first surface and spaced from each other. The anti-reflection layer is disposed on the doping block layer and the semiconductor substrate. The front electrodes penetrate the anti-reflection layer and are arranged on the doping block layers. The back electrode layer is disposed on a second surface of the semiconductor substrate.

Abstract: An embodiment of the present invention provides an electronic device package, which includes a chip having a first surface and an opposite second surface and a trench extending into a body of the chip along a direction from the second surface to the first surface, wherein a bottom portion of the trench includes at least two contact holes.

Abstract: A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.

Abstract: A power MOSFET package includes a semiconductor substrate having opposite first and second surfaces, having a first conductivity type, and forming a drain region, a doped region extending downward from the first surface and having a second conductivity type, a source region in the doped region and having the first conductivity type, a gate overlying or buried under the first surface, wherein a gate dielectric layer is between the gate and the semiconductor substrate, a first conducting structure overlying the semiconductor substrate, having a first terminal, and electrically connecting the drain region, a second conducting structure overlying the semiconductor substrate, having a second terminal, and electrically connecting the source region, a third conducting structure overlying the semiconductor substrate, having a third terminal, and electrically connecting the gate, wherein the first, the second, and the third terminals are substantially coplanar, and a protection layer between the semiconductor substrat

Abstract: The present disclosure relates to a switch circuit. The switch circuit comprises: a plurality of storing elements and a plurality of switch elements. The plurality of switch elements coupled the plurality of storing elements for generating a step-down mode. Moreover, the switch elements, controllers and parts of resistors in the present disclosure are integrated in an integrated circuit so as to effectively reduce size and weight of the driving circuit, advance the circuit suitability, and decrease the development cost of the circuit.

Abstract: A chip package is disclosed. The package includes a carrier substrate, at least two semiconductor chips, a fill material layer, a protective layer, and a plurality of conductive bumps. The carrier substrate includes a grounding region. The semiconductor chips are disposed overlying the grounding region of the carrier substrate. Each semiconductor chip includes at least one signal pad and includes at least one grounding pad electrically connected to the grounding region. The fill material layer is formed overlying the carrier substrate and covers the semiconductor chips. The protective layer covers the fill material layer. The plurality of conductive bumps is disposed overlying the protective layer and is electrically connected to the semiconductor chips. A fabrication method of the chip package is also disclosed.