Patents by Inventor Wei-Ming Liao

Wei-Ming Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240141922
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Application
    Filed: January 9, 2024
    Publication date: May 2, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240138098
    Abstract: A centrifugal heat dissipation fan of a portable electronic device. The centrifugal heat dissipation fan includes a hub, multiple metal blades, and at least one ring. The metal blades are disposed surrounding the hub. The metal blades include multiple radial dimensions, and the structure of the metal blade with a shorter radial dimension is a part of the structure of the metal blade with a longer radial dimension. The metal blades having different radial dimensions form at least two ring areas, and the distribution numbers of the metal blades in the at least two ring areas are different from each other. The ring surrounds the hub and connects the metal blades.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 25, 2024
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Yu-Ming Lin
  • Patent number: 11968800
    Abstract: A centrifugal heat dissipation fan including a housing and an impeller is provided. The housing has at least one inlet disposed along an axis and at least one first outlet and a second outlet located in different radial directions, wherein the first outlet and the second outlet are opposite to and separated from each other. The impeller is disposed in the housing along the axis. A heat dissipation system of an electronic device is also provided.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Kuang-Hua Lin, Sheng-Yan Chen
  • Patent number: 11950491
    Abstract: A semiconductor mixed material comprises an electron donor, a first electron acceptor and a second electron acceptor. The first electron donor is a conjugated polymer. The energy gap of the first electron acceptor is less than 1.4 eV. At least one of the molecular stackability, ?-?*stackability, and crystallinity of the second electron acceptor is smaller than the first electron acceptor. The electron donor system is configured to be a matrix to blend the first electron acceptor and the second electron acceptor. The present invention also provides an organic electronic device including the semiconductor mixed material.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: April 2, 2024
    Assignee: RAYNERGY TEK INCORPORATION
    Inventors: Yi-Ming Chang, Chuang-Yi Liao, Wei-Long Li, Yu-Tang Hsiao, Chun-Chieh Lee, Chia-Hua Li, Huei-Shuan Tan
  • Patent number: 11935780
    Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 19, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chuan-Lin Hsiao, Wei-Ming Liao
  • Patent number: 11913472
    Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.
    Type: Grant
    Filed: April 6, 2021
    Date of Patent: February 27, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240047265
    Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 8, 2024
    Inventors: Chuan-Lin HSIAO, Wei-Ming LIAO
  • Patent number: 11659707
    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate having an active region surrounded by an isolation layer; forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer; forming a bottom work-function layer in the third trench and the fourth trench, respectively; forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches; forming a top work-function layer on the middle work-function layer; and forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: May 23, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Publication number: 20230141995
    Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 11, 2023
    Inventors: Chuan-Lin HSIAO, Wei-Ming LIAO
  • Patent number: 11582844
    Abstract: The invention provides a detection circuit for detecting light-off modes performed by a silicon-controlled dimmer which comprises a voltage detection circuit receiving an output signal and generating a voltage detection signal according to the output signal, and a delay circuit connected to the voltage detection circuit, receiving the voltage detection signal, and delaying the voltage detection signal in order to output a detection signal. The invention detects the output signal through the voltage detection circuit, and delays the detected voltage detection signal to output the corresponding detection signal, and then the detection signal effectively distinguishes the light-off modes performed by the silicon-controlled dimmer to meet requirements of users.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: February 14, 2023
    Assignee: SHANGHAI SILICON DRIVER SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Yue Zheng, Wei-Ming Liao, Xiao-Bo Hu
  • Patent number: 11570861
    Abstract: The invention provides an LED drive power supply and a controller thereof. The controller comprises a ground terminal, a sampling terminal, and a power supply terminal. The ground terminal and an output ground of a power supply module have different potentials. A drain of a power switching transistor is coupled to a positive output terminal of the power supply module, a source of the power switching transistor and the sampling terminal are coupled to a first terminal of a sampling resistor, and a second terminal of the sampling resistor is coupled to the ground terminal. The controller further includes a logic control circuit determining whether a sampling voltage input by the sampling terminal is zero; a driver generating a first driving signal to the power switching transistor; and a bias circuit configured to receive a power supply voltage.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: January 31, 2023
    Assignee: SHANGHAI SILICON DRIVER SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Yue Zheng, Wei-Ming Liao, Xiao-Bo Hu
  • Patent number: 11488964
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Patent number: 11482419
    Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 25, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jhen-Yu Tsai, Tseng-Fu Lu, Wei-Ming Liao
  • Publication number: 20220216213
    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate having an active region surrounded by an isolation layer; forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer; forming a bottom work-function layer in the third trench and the fourth trench, respectively; forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches; forming a top work-function layer on the middle work-function layer; and forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Ching-Chia HUANG, Wei-Ming LIAO
  • Patent number: 11315930
    Abstract: A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Publication number: 20210335794
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 28, 2021
    Inventors: Ching-Chia HUANG, Wei-Ming LIAO
  • Publication number: 20210298142
    Abstract: The invention provides an LED drive power supply and a controller thereof. The controller comprises a ground terminal, a sampling terminal, and a power supply terminal. The ground terminal and an output ground of a power supply module have different potentials. A drain of a power switching transistor is coupled to a positive output terminal of the power supply module, a source of the power switching transistor and the sampling terminal are coupled to a first terminal of a sampling resistor, and a second terminal of the sampling resistor is coupled to the ground terminal. The controller further includes a logic control circuit determining whether a sampling voltage input by the sampling terminal is zero; a driver generating a first driving signal to the power switching transistor; and a bias circuit configured to receive a power supply voltage.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 23, 2021
    Inventors: Yue ZHENG, Wei-Ming LIAO, Xiao-Bo HU
  • Publication number: 20210265361
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Inventors: Ching-Chia HUANG, Wei-Ming LIAO
  • Patent number: 11101273
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 24, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Patent number: D1023729
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: April 23, 2024
    Assignee: YOKE INDUSTRIAL CORP.
    Inventors: Wei-Chieh Hung, Wen-Ming Liao, Tzu-Lun Weng