Patents by Inventor Wei-Ming Liao

Wei-Ming Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11488964
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Grant
    Filed: July 9, 2021
    Date of Patent: November 1, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Patent number: 11482419
    Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: October 25, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Jhen-Yu Tsai, Tseng-Fu Lu, Wei-Ming Liao
  • Publication number: 20220320726
    Abstract: An electronic device is provided. The electronic device includes a plurality of main device antennas, a switch, and a processor. The switch enables at least one of the main device antennas. The processor is electrically connected to the switch and controls the switch to switch the enabled main device antenna based on a usage status of the electronic device.
    Type: Application
    Filed: March 18, 2022
    Publication date: October 6, 2022
    Inventors: Chien-Ming HSU, Kuo-Chu LIAO, Wei-Cheng LO
  • Publication number: 20220273972
    Abstract: A fall arrest device includes a braking device, a frame, and a rotating member connected to the frame. The rotating member includes a main body and a plurality of pawls which are pivotally connected to a mounting portion of the main body. Each of the pawls has an abutting portion, a pivot, and a body portion. The braking device has a plurality of abutted portions. When a rotation speed of the rotating member is greater than or equal to a predetermined rotation speed, the abutting portions abut against the abutted portions to stop a rotation of the rotating member. When the rotation speed of the rotating member is smaller than the predetermined rotation speed, the body portion of each of the pawls touches a periphery of the abutted portions and swings as an outer diameter of the abutted portions of the braking device changes.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Applicant: YOKE INDUSTRIAL CORP.
    Inventors: Wei-Chieh Hung, Wen-Ming Liao
  • Publication number: 20220229477
    Abstract: A heat dissipation system of a portable electronic device is provided. The heat dissipation system includes a body and at least one fan. A heat source of the portable electronic device is disposed in the body. The fan is a centrifugal fan disposed in the body. The fan has at least one flow inlet, at least one flow outlet, and at least one spacing portion. The flow outlet faces toward the heat source, and the spacing portion surrounds the flow inlet and abuts against the body, so as to isolate the flow inlet and the heat source in two spaces independent of each other in the body.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 21, 2022
    Applicant: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Kuang-Hua Lin, Chun-Chieh Wang, Shu-Hao Kuo
  • Patent number: 11387124
    Abstract: Provided is a wafer container including a frame having a first sidewall and a second sidewall extending along a YZ plane; a plurality of first support structures disposed on the first sidewall and arranged along a Z direction; and a plurality of second support structures disposed on the second sidewall and arranged along the Z direction. One of the plurality of first support structures is horizontally aligned with a corresponding second support structure to constitute a wafer holder. The wafer holder includes a plurality of island structures to hold a wafer in a XY plane, and the plurality of island structures are separated to each other along a X direction. A method for holding at least one wafer is also provided.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: July 12, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Kang Liu, Chi-Chung Jen, Jui-Ming Huang, Wan-Ting Liao
  • Publication number: 20220216213
    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate having an active region surrounded by an isolation layer; forming a first trench and a second trench in the active region, and a third trench and a fourth trench in the isolation layer; forming a bottom work-function layer in the third trench and the fourth trench, respectively; forming a middle work-function layer on the bottom work-function layer and in the first and the second trenches; forming a top work-function layer on the middle work-function layer; and forming a capping layer on the top work-function layer that fills a remaining region of the first, the second, the third and the fourth trenches.
    Type: Application
    Filed: March 22, 2022
    Publication date: July 7, 2022
    Inventors: Ching-Chia HUANG, Wei-Ming LIAO
  • Patent number: 11315930
    Abstract: A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: April 26, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Publication number: 20210335794
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 28, 2021
    Inventors: Ching-Chia HUANG, Wei-Ming LIAO
  • Publication number: 20210298142
    Abstract: The invention provides an LED drive power supply and a controller thereof. The controller comprises a ground terminal, a sampling terminal, and a power supply terminal. The ground terminal and an output ground of a power supply module have different potentials. A drain of a power switching transistor is coupled to a positive output terminal of the power supply module, a source of the power switching transistor and the sampling terminal are coupled to a first terminal of a sampling resistor, and a second terminal of the sampling resistor is coupled to the ground terminal. The controller further includes a logic control circuit determining whether a sampling voltage input by the sampling terminal is zero; a driver generating a first driving signal to the power switching transistor; and a bias circuit configured to receive a power supply voltage.
    Type: Application
    Filed: March 16, 2021
    Publication date: September 23, 2021
    Inventors: Yue ZHENG, Wei-Ming LIAO, Xiao-Bo HU
  • Publication number: 20210265361
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Application
    Filed: February 25, 2020
    Publication date: August 26, 2021
    Inventors: Ching-Chia HUANG, Wei-Ming LIAO
  • Patent number: 11101273
    Abstract: A method of manufacturing a semiconductor structure includes: receiving a substrate having an active region and a non-active region adjacent to the active region; forming an etch stop layer over the non-active region of the substrate, in which the etch stop layer is oxide-free; forming an isolation over the etch stop layer; removing a portion of the active region and a portion of the isolation to form a first trench in the active region and a second trench over the etch stop layer, respectively, in which a thickness of the etch stop layer beneath the second trench is greater than a depth difference between the first trench and the second trench; forming a dielectric layer in the first trench; and filling a conductive material on the dielectric layer in the first trench and in the second trench. A semiconductor structure is also provided.
    Type: Grant
    Filed: February 25, 2020
    Date of Patent: August 24, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Wei-Ming Liao
  • Publication number: 20210257372
    Abstract: A semiconductor structure includes a substrate, a first word line structure, a second word line structure, a third word line structure, and a fourth word line structure. The substrate has an active region surrounded by an isolation structure. The first and second word line structures are disposed in the active region and separated from each other. The third and fourth word line structures are disposed in the isolation structure, and each of the third and the fourth word line structures includes a bottom work-function layer, a middle work-function layer on the bottom work-function layer, and a top work function layer on the work-function middle layer. The middle work-function layer has a work-function that is higher than a work-function of the top work-function layer and a work-function of the bottom work-function layer.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 19, 2021
    Inventors: Ching-Chia HUANG, Wei-Ming LIAO
  • Publication number: 20210082705
    Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: JHEN-YU TSAI, TSENG-FU LU, WEI-MING LIAO
  • Patent number: 10937886
    Abstract: A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.
    Type: Grant
    Filed: March 11, 2019
    Date of Patent: March 2, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu, Wei-Ming Liao
  • Publication number: 20210029792
    Abstract: The invention provides a detection circuit for detecting light-off modes performed by a silicon-controlled dimmer which comprises a voltage detection circuit receiving an output signal and generating a voltage detection signal according to the output signal, and a delay circuit connected to the voltage detection circuit, receiving the voltage detection signal, and delaying the voltage detection signal in order to output a detection signal. The invention detects the output signal through the voltage detection circuit, and delays the detected voltage detection signal to output the corresponding detection signal, and then the detection signal effectively distinguishes the light-off modes performed by the silicon-controlled dimmer to meet requirements of users.
    Type: Application
    Filed: July 23, 2020
    Publication date: January 28, 2021
    Inventors: Yue ZHENG, Wei-Ming LIAO, Xiao-Bo HU
  • Patent number: 10903080
    Abstract: The present disclosure provides a transistor device and a method for preparing the same. The transistor device includes an isolation structure disposed in a substrate, an active region disposed in the substrate and surrounded by the isolation structure, a first upper gate disposed over the active region and a portion of the isolation structure, a source/drain disposed at two sides of the gate, and a pair of first lower gates disposed under the first upper gate and isolated from the active region by the isolation structure. In some embodiments, the pair of first lower gates extend in a first direction, the first upper gate extends in a second direction, and the first direction and the second direction are different.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 26, 2021
    Assignee: Nanya Technology Corporation
    Inventors: Jhen-Yu Tsai, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10825898
    Abstract: The semiconductor layout structure includes an active region surrounded by an isolation structure, at least one first gate structure disposed over the active region and the isolation structure, at least one second gate structure disposed over the active region and the isolation structure, and a plurality of source/drain regions disposed in the active region. The active region includes two first regions, a second region disposed between the two first regions, a third region disposed between one of the first region and the second region, and a fourth region disposed between the other first region and the second region.
    Type: Grant
    Filed: December 19, 2019
    Date of Patent: November 3, 2020
    Assignee: Nanya Technology Corporation
    Inventors: Jhen-Yu Tsai, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10825931
    Abstract: A semiconductor device includes a semiconductor substrate, a dielectric layer, a gate structure, a source semiconductor feature, and a drain semiconductor feature. The semiconductor substrate has an active area and a shallow trench isolation (STI) structure surrounding the active area. The semiconductor substrate includes a protrusion structure in the active area and has an undercut at a periphery of the active area. The dielectric layer overlays the protrusion structure of the semiconductor substrate and fills at least a portion of the undercut of the protrusion structure. The gate structure crosses over the protrusion structure. The source semiconductor feature and the drain semiconductor feature are located in the active area and positioned at opposite sides of the gate structure.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ching-Chia Huang, Tseng-Fu Lu, Wei-Ming Liao
  • Patent number: 10818800
    Abstract: The present disclosure provides a semiconductor structure including a substrate, a bottom gate portion disposed in the substrate, a top gate portion stacked over the bottom gate portion, a first channel layer sandwiched between the top gate portion and the bottom gate portion, and a source/drain region disposed in the substrate at two opposite sides of the top gate portion.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 27, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Cheng-Hsien Hsieh, Tseng-Fu Lu, Jhen-Yu Tsai, Ching-Chia Huang, Wei-Ming Liao