Patents by Inventor Wei-Ming You
Wei-Ming You has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10062787Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.Type: GrantFiled: January 25, 2017Date of Patent: August 28, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Ting Hsiao, Cheng-Ta Wu, Lun-Kuang Tan, Liang-Yu Yen, Ting-Chun Wang, Tsung-Han Wu, Wei-Ming You
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Publication number: 20180012963Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.Type: ApplicationFiled: September 12, 2017Publication date: January 11, 2018Inventors: CHENG-TA WU, YI-HSIEN LEE, WEI-MING YOU, TING-CHUN WANG
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Patent number: 9768261Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.Type: GrantFiled: April 17, 2015Date of Patent: September 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheng-Ta Wu, Yi-Hsien Lee, Wei-Ming You, Ting-Chun Wang
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Patent number: 9716090Abstract: A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.Type: GrantFiled: June 27, 2016Date of Patent: July 25, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Hong-Yi Wu, Shiu-Ko Jangjian, Wei-Ming You, Ting-Chun Wang
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Patent number: 9697989Abstract: The present disclosure provides a method for generating a parameter pattern including: performing a plurality of measurements upon a plurality of regions on a surface of a workpiece to obtain a plurality of measured results; and deriving a parameter pattern according to the plurality of measured results by a computer; wherein the parameter pattern includes a plurality of regional parameter values corresponding to each of the plurality of regions on the surface of the workpiece. The present disclosure provides a Feed Forward semiconductor manufacturing method including: forming a layer with a desired pattern on a surface of a workpiece; deriving a control signal including a parameter pattern according to spatial dimension measurements against the layer with the desired pattern distributed over a plurality of regions of the surface of the workpiece; and performing an ion implantation on the surface of the workpiece according to the control signal.Type: GrantFiled: February 26, 2015Date of Patent: July 4, 2017Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventors: Cheng-Ta Wu, Tsung Han Wu, Yao-Wen Hsu, Lun-Kuang Tan, Wei-Ming You, Ting-Chun Wang
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Publication number: 20170133509Abstract: A FinFET includes a fin structure, a gate, a source-drain region and an inter layer dielectric (ILD). The gate crosses over the fin structure. The source-drain region is in the fin structure. The ILD is laterally adjacent to the gate and includes a dopant, in which a dopant concentration of the ILD adjacent to the gate is lower than a dopant concentration of the ILD away from the gate.Type: ApplicationFiled: January 25, 2017Publication date: May 11, 2017Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Ting HSIAO, Cheng-Ta WU, Lun-Kuang TAN, Liang-Yu YEN, Ting-Chun WANG, Tsung-Han WU, Wei-Ming YOU
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Patent number: 9577102Abstract: A method of forming a gate includes: forming a dummy gate; forming an inter layer dielectric (ILD) laterally adjacent to the dummy gate; doping a dopant into the dummy gate and the ILD, in which a surface dopant concentration of the dummy gate is lower than a surface dopant concentration of the ILD; removing the dummy gate to form a cavity after doping the dopant into the dummy gate and the ILD; and forming the gate in the cavity.Type: GrantFiled: September 25, 2015Date of Patent: February 21, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yu-Ting Hsiao, Cheng-Ta Wu, Lun-Kuang Tan, Liang-Yu Yen, Ting-Chun Wang, Tsung-Han Wu, Wei-Ming You
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Publication number: 20170047420Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.Type: ApplicationFiled: October 27, 2016Publication date: February 16, 2017Inventors: Sheng-Wen Chen, Yu-Ting Lin, Che-Hao Chang, Wei-Ming You, Ting-Chun Wang
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Publication number: 20170025535Abstract: A method for manufacturing a semiconductor device is provided including forming one or more fins over a substrate and forming an isolation insulating layer over the one or more fins. A dopant is introduced into the isolation insulating layer. The isolation insulating layer containing the dopant is annealed, and a portion of the oxide layer is removed so as to expose a portion of the fins.Type: ApplicationFiled: July 21, 2015Publication date: January 26, 2017Inventors: Cheng-Ta WU, Ting-Chun WANG, Wei-Ming YOU, J.W. WU
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Patent number: 9508548Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.Type: GrantFiled: March 31, 2014Date of Patent: November 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Wen Chen, Yu-Ting Lin, Che-Hao Chang, Wei-Ming You, Ting-Chun Wang
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Publication number: 20160308059Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes: a substrate; a fin structure protruding from the substrate, the fin structure extending along a first direction; isolation features disposed on both sides of the fin structure; a gate structure over the fin structure and extending on the isolation features along a second direction perpendicular to the first direction; and wherein the gate structure includes a first segment and a second segment, the second segment being over the first segment and including a greater dimension in the first direction than that of the first segment.Type: ApplicationFiled: April 17, 2015Publication date: October 20, 2016Inventors: CHENG-TA WU, YI-HSIEN LEE, WEI-MING YOU, TING-CHUN WANG
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Publication number: 20160307895Abstract: A FinFET structure includes a substrate, a plurality of stripes, a metal gate and an oxide material. The stripes are on the substrate. The metal gate is on a sidewall and a top surface of one of the stripes. The oxide material is between the metal gate and the stripes. An average roughness of an interface between the metal gate and the oxide material is in a range of from about 0.1 nm to about 0.2 nm.Type: ApplicationFiled: June 27, 2016Publication date: October 20, 2016Inventors: CHENG-TA WU, CHENG-WEI CHEN, HONG-YI WU, SHIU-KO JANGJIAN, WEI-MING YOU, TING-CHUN WANG
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Publication number: 20160254122Abstract: The present disclosure provides a method for generating a parameter pattern including: performing a plurality of measurements upon a plurality of regions on a surface of a workpiece to obtain a plurality of measured results; and deriving a parameter pattern according to the plurality of measured results by a computer; wherein the parameter pattern includes a plurality of regional parameter values corresponding to each of the plurality of regions on the surface of the workpiece. The present disclosure provides a Feed Forward semiconductor manufacturing method including: forming a layer with a desired pattern on a surface of a workpiece; deriving a control signal including a parameter pattern according to spatial dimension measurements against the layer with the desired pattern distributed over a plurality of regions of the surface of the workpiece; and performing an ion implantation on the surface of the workpiece according to the control signal.Type: ApplicationFiled: February 26, 2015Publication date: September 1, 2016Inventors: CHENG-TA WU, TSUNG HAN WU, YAO-WEN HSU, LUN-KUANG TAN, WEI-MING YOU, TING-CHUN WANG
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Patent number: 9406675Abstract: A semiconductor structure and a method for forming the same are provided. The method includes providing a substrate, forming a fin structure extruding from the substrate, forming shallow trench isolations over the substrate, and forming an oxide material over the fin structure. The method further includes forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer over the oxide material, wherein the forming a carbon-doped amorphous silicon layer or a carbon-doped poly silicon layer includes doping carbon in a range of from about 5E19/cm3 to about 1E22/cm3.Type: GrantFiled: March 16, 2015Date of Patent: August 2, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Cheng-Ta Wu, Cheng-Wei Chen, Hong-Yi Wu, Shiu-Ko Jangjian, Wei-Ming You, Ting-Chun Wang
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Publication number: 20150372099Abstract: A substrate is provided. The substrate has a source/drain region formed therein and a dielectric layer formed thereover. A contact hole is etched in the dielectric layer to expose a portion of the source/drain region. A metal material is formed on the source/drain region exposed by the opening. A first annealing process is performed to facilitate a reaction between the metal material and the portion of the source/drain region disposed therebelow, thereby forming a metal silicide in the substrate. The first annealing process is a spike annealing process. A remaining portion of the metal material is removed after the performing of the first annealing process. Thereafter, a second annealing process is performed. Thereafter, a contact is formed in the contact hole, the contact being formed on the metal silicide.Type: ApplicationFiled: June 19, 2014Publication date: December 24, 2015Inventors: Sheng-Wen Chen, Yu-Ting Lin, Jemmy Tsai, Wei-Ming You, Ting-Chun Wang
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Publication number: 20150279954Abstract: A semiconductor device having a high-k gate dielectric, and a method of manufacture, is provided. A gate dielectric layer is formed over a substrate. An interfacial layer may be interposed between the gate dielectric layer and the substrate. A barrier layer, such as a TiN layer, having a higher concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer is formed. The barrier layer may be formed by depositing, for example, a TiN layer and performing a nitridation process on the TiN layer to increase the concentration of nitrogen along an interface between the barrier layer and the gate dielectric layer. A gate electrode is formed over the barrier layer.Type: ApplicationFiled: March 31, 2014Publication date: October 1, 2015Inventors: Sheng-Wen Chen, Yu-Ting Lin, Che-Hao Chang, Wei-Ming You, Ting-Chun Wang
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Patent number: 8860101Abstract: A system and method for reducing cross-talk between photosensitive diodes is provided. In an embodiment an isolation region comprising a first concentration of dopants is located between the photosensitive diodes. The photosensitive diodes have a second concentration of dopants that is less than the first concentration of dopants, which helps to prevent diffusion from the photosensitive diodes to form a potential path for undesired cross-talk between the photosensitive diodes.Type: GrantFiled: February 27, 2012Date of Patent: October 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Lan Fang Chang, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Chih-Kang Chao, Fu-Sheng Guo
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Patent number: 8652868Abstract: An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.Type: GrantFiled: March 1, 2012Date of Patent: February 18, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Shen Shih, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Kuo-Cheng Lee, Yen-Hsung Ho
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Patent number: 8628998Abstract: A method includes performing a grinding on a backside of a semiconductor substrate. An image sensor is disposed on a front side of the semiconductor substrate. An impurity is doped into a surface layer of the backside of the semiconductor substrate to form a doped layer. A multi-cycle laser anneal is performed on the doped layer.Type: GrantFiled: May 22, 2012Date of Patent: January 14, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ting Lin, Cheng-Jung Sung, Yu-Sheng Wang, Shiu-Ko JangJian, Wei-Ming You, Chih-Cherng Jeng, Ching-Hwanq Su
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Publication number: 20130230941Abstract: An implanting method for forming a photodiode comprises providing a substrate with a first conductivity, growing an epitaxial layer on the substrate, implanting ions with a second conductivity in the epitaxial layer from a front side of the substrate and implanting ions with the first conductivity in the epitaxial layer from the front side of the substrate to form a photo active region adjacent to the front side and a photo inactive region underneath the photo active region. By employing the implanting method, an average doping density of the photo active region is approximately ten times more than an average doping density of the photo inactive region.Type: ApplicationFiled: March 1, 2012Publication date: September 5, 2013Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Shen Shih, Ching-Hwanq Su, Wei-Ming You, Chih-Cherng Jeng, Kuo-Cheng Lee, Yen-Hsung Ho