Abstract: A processor and a method for executing a matrix multiplication operation on a processor. A specific implementation of the processor includes a data bus and an array processor having k processing units. The data bus is configured to sequentially read n columns of row vectors from an M×N multiplicand matrix and input same to each processing unit in the array processor, read an n×k submatrix from an N×K multiplier matrix and input each column vector of the submatrix to a corresponding processing unit in the array processor, and output a result obtained by each processing unit after executing a multiplication operation. Each processing unit in the array processor is configured to execute in parallel a vector multiplication operation on the input row and column vectors. Each processing unit includes a Wallace tree multiplier having n multipliers and n?1 adders. This implementation improves the processing efficiency of a matrix multiplication operation.

Abstract: The present application discloses a processor and a method for executing an instruction on a processor. A specific implementation of the processor includes: a host interaction device, an instruction control device, an off-chip memory, an on-chip cache and an array processing device, wherein the host interaction device is configured to exchange data and instructions with a host connected with the processor, wherein the exchanged data has a granularity of a matrix; the off-chip memory is configured to store a matrix received from the host, on which a matrix operation is to be performed; and the instruction control device is configured to convert an external instruction received from the host to a series of memory access instructions and a series of computing instructions and execute the converted instructions. The implementation can improve the execution efficiency of a deep learning algorithm.

Abstract: A method and a device for realizing compatibility of secondary videos. The method comprises: connecting a first terminal to a second terminal through a hub, the first terminal and the second terminal supporting for different types of secondary videos, the number of the first terminal being one or more, and the number of the second terminal being one or more; converting signaling type of the secondary video signal transmitted through the hub between the first terminal and the second terminal and converting a type of the secondary video media code stream transmitted through the hub between the first terminal and the second terminal, to realize compatibility of the different types of secondary videos between the first terminal and the second terminal.

Abstract: The present invention relates to an azetidine derivative for use as a Janus kinase (JAK) inhibitor, a drug composition comprising same, a preparation method therefor, and a use thereof in the treatment of JAK-related diseases comprising, for example, inflammatory diseases, autoimmune diseases, and cancers.

Abstract: Disclosed are a control method, system, and apparatus for conference terminal rights, and a storage medium. The method include: judging whether access resources required by a first conference terminal for accessing a conference are sufficient before the first conference terminal accesses the conference, wherein conference terminals accessing the conference have different priorities; and releasing access resources of a second conference terminal having a priority lower than a priority of the first conference terminal and allocating the released access resources to the first conference terminal in a case that the access resources required by the first conference terminal for accessing the conference are not sufficient.

Abstract: The present disclosure discloses a method and an apparatus for authenticating a user. A specific embodiment of the method comprises: receiving an authentication request sent by a user terminal, wherein the authentication request comprises a user identification of a user of the user terminal and operation information related to user operation; determining whether the user operation matches a preset to-be-authenticated operation according to the user identification and the operation information; sending voicing material to the user terminal for reading by the user in response to determining that the user operation matches the preset to-be-authenticated operation, so that the user terminal acquires corresponding authentication voice of the user; receiving the authentication voice sent by the user terminal; and authenticating the user according to the user identification and the authentication voice.

Abstract: The present application discloses a method and apparatus for processing a data sequence. A specific implementation of the method includes: receiving an inputted to-be-processed data sequence; copying a weight matrix in a recurrent neural network model to an embedded block random access memory (RAM) of a field-programmable gate array (FPGA); processing sequentially each piece of to-be-processed data in the to-be-processed data sequence by using an activation function in the recurrent neural network model and the weight matrix stored in the embedded block RAM; and outputting a processed data sequence corresponding to the to-be-processed data sequence. This implementation improves the data sequence processing efficiency of the recurrent neural network model.

Abstract: The present application discloses a method, system and apparatus for storing a website private key plaintext. A specific implementation of the method includes: receiving a public key sent from a terminal configured to perform encryption and decryption, wherein the public key is generated at random by the terminal; encrypting a website private key plaintext by using the public key to generate a website private key ciphertext, wherein the website private key plaintext is pre-acquired; and sending the website private key ciphertext to the terminal, so that the terminal decrypts the website private key ciphertext by using the private key to generate the website private key plaintext and store the website private key plaintext in the terminal. This implementation improves the security of storage of the website private key plaintext.

Abstract: The present application discloses an RSA decryption processor and a method for controlling an RSA decryption processor. A specific implementation of the processor includes a memory, a control component, and a parallel processor. The memory is configured to store decryption parameters comprising a private key. The control component is configured to receive a ciphertext set, and send a decryption signal comprising the ciphertext set to the parallel processor. The parallel processor is configured to: read a decryption parameter from the memory in response to receiving the decryption signal, and use at least one modular exponentiation circuit unit in the parallel processor to perform in parallel a modular exponentiation operation on ciphertexts in the ciphertext set by using the read decryption parameter, to obtain plaintexts corresponding to the ciphertexts. This implementation improves the efficiency of RSA decryption.

Abstract: The present application discloses a data processing method and apparatus. A specific implementation of the method includes: receiving floating point data sent from an electronic device; converting the received floating point data into fixed point data according to a data length and a value range of the received floating point data; performing calculation on the obtained fixed point data according to a preset algorithm to obtain result data in a fixed point form; and converting the obtained result data in the fixed point form into result data in a floating point form and sending the result data in the floating point form to the electronic device. This implementation improves the data processing efficiency.

Abstract: A processor and a method for executing a matrix multiplication operation on a processor. A specific implementation of the processor includes a data bus and an array processor having k processing units. The data bus is configured to sequentially read n columns of row vectors from an M×N multiplicand matrix and input same to each processing unit in the array processor, read an n×k submatrix from an N×K multiplier matrix and input each column vector of the submatrix to a corresponding processing unit in the array processor, and output a result obtained by each processing unit after executing a multiplication operation. Each processing unit in the array processor is configured to execute in parallel a vector multiplication operation on the input row and column vectors. Each processing unit includes a Wallace tree multiplier having n multipliers and n-1 adders. This implementation improves the processing efficiency of a matrix multiplication operation.

Abstract: Disclosed are apparatuses including a cable header block with apertures for floating inserts and a cover plate. The cable header block includes an aperture pattern that matches a pattern of connector terminals. The floating inserts fit in the apertures of the cable header block. The cover plate can also include a through-hole pattern that matches the aperture pattern. Also, each of the through-holes can include a first geometric shape larger than a cross-section of a cable terminal end and a second geometric shape adjacent to the first shape that is smaller than the cross-section of the cable terminal end. The cover plate retains the floating inserts within the apertures. Also, the cover plate aligns the first geometric shape over the floating inserts when the fastener is in a first position and aligns the second geometric shape over the floating inserts when the fastener is in a second position.

Abstract: Embodiments of the present invention relate to a method, apparatus and computer product for managing memory space. In one aspect of the present invention, there is provided a method for managing memory space that is organized into pages, the pages being divided into a plurality of page sets, each page set being associated with one of a plurality of upper-layer systems, by: performing state monitoring to the plurality of upper-layer systems to assign priorities to the plurality of upper-layer systems; and determining an order of releasing the pages of the memory space based on the priorities of the plurality of upper-layer systems with the page sets as units. Other aspects and embodiments of invention are also disclosed.

Abstract: The present disclosure provides a method and apparatus for processing a floating point number matrix, an apparatus and a computer readable storage medium. In embodiments of the present disclosure, the minimum value of the floating point number model matrix and the maximum value of the floating point number model matrix are obtained according to a floating point number model matrix to be compressed, and then, compression processing is performed for the floating point number model matrix to obtain the fixed point number model matrix according to the bit width, the minimum value of the floating point number model matrix and the maximum value of the floating point number model matrix. The compression processing is performed for the floating point number model matrix of the deep learning model by a fixed point method, to obtain the fixed point number model matrix and reduce the storage space and amount of operation of the deep learning model.

Abstract: The present application discloses a processor and a method for executing an instruction on a processor. The method includes: fetching a to-be-executed instruction, the instruction comprising a source address field, a destination address field, an operation type field, and an operation parameter field; determining, in at least one execution unit, an execution unit controlled by a to-be-generated control signal according to the operation type field, determining a source address and a destination address of data operated by the execution unit controlled by the to-be-generated control signal according to the source address field and the destination address field, and determining a data amount of the data operated by the execution unit controlled by the to-be-generated control signal according to the operation parameter field; generating the control signal; and controlling, by using the control signal, the execution unit in the at least one execution unit to execute an operation.

Abstract: The present application discloses a processor and a method for executing an instruction on a processor. A specific implementation of the processor includes: a host interaction device, an instruction control device, an off-chip memory, an on-chip cache and an array processing device, wherein the host interaction device is configured to exchange data and instructions with a host connected with the processor, wherein the exchanged data has a granularity of a matrix; the off-chip memory is configured to store a matrix received from the host, on which a matrix operation is to be performed; and the instruction control device is configured to convert an external instruction received from the host to a series of memory access instructions and a series of computing instructions and execute the converted instructions. The implementation can improve the execution efficiency of a deep learning algorithm.

Abstract: The present application discloses a data processing method and apparatus. A specific embodiment of the method includes: preprocessing received to-be-processed input data; obtaining a storage address of configuration parameters of the to-be-processed input data based on a result of the preprocessing and a result obtained by linearly fitting an activation function, the configuration parameters being preset according to curve characteristics of the activation function; acquiring the configuration parameters of the to-be-processed input data according to the storage address; and processing the result of the preprocessing of the to-be-processed input data based on the configuration parameters of the to-be-processed input data and a preset circuit structure, to obtain a processing result.

Abstract: A compound of Formula (I), or a pharmaceutically acceptable salt thereof, is provided that has been shown to be useful for treating a PRC2-mediated disease or disorder: wherein R1, R2, R3, R4, R5, and n are as defined herein.

Abstract: In one implementation, an apparatus includes a securing component configured to attach the line card ejector to a chassis of a network communication device, prevent removal of a line card from the chassis when the securing component is in a first configuration, and allow removal of the line card from the chassis when the securing component is in a second configuration. The apparatus also includes an ejection component configured to facilitate insertion and removal of the line card from the chassis of the network communication device. The apparatus further includes a sensor component configured to detect an imminent removal of the line card from the chassis of the network communication device.

Abstract: A device and system for supporting a patient or an object in an examination is provided. The supporting system may include a portion for supporting the body of a patient and/or a head supporting device. The portion for supporting the body may move in one or more directions. The head supporting device may be adjust to meet requirements of imaging when the patient or the object is supine or prone.