Patents by Inventor Wei-Sheng Yun

Wei-Sheng Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210135009
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure formed over a substrate. The semiconductor device structure includes a first gate structure formed over the first fin structure, and the first gate structure includes a first portion of a gate dielectric layer and a first portion of a filling layer. The semiconductor device structure also includes a second gate structure formed over the second fin structure, and a first isolation sealing layer between the first gate structure and the second gate structure. The first isolation sealing layer is in direct contact with the first portion of the gate dielectric layer and the first portion of the filling layer.
    Type: Application
    Filed: June 18, 2020
    Publication date: May 6, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Chao LIN, Wei-Sheng YUN, Tung-Ying LEE
  • Patent number: 10991811
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a plurality of nanowires over an input-output region, and a protective layer surrounding the nanowires. The protective layer is made of silicon, silicon germanium, silicon oxide, silicon nitride, silicon sulfide, or a combination thereof. The semiconductor device structure also includes a high-k dielectric layer surrounding the protective layer, and a gate electrode surrounding the high-k dielectric layer. The semiconductor device structure further includes a source/drain portion adjacent to the gate electrode, and an interlayer dielectric layer over the source/drain portion.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: April 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee, Chih-Chieh Yeh
  • Patent number: 10978422
    Abstract: A method includes forming a fin structure over a semiconductor substrate; forming a liner covering the fin structure; etching back the liner to expose an upper portion of the fin structure; forming a spacer covering the upper portion of the fin structure; etching the liner to expose a middle portion of the fin structure, wherein the remaining liner covers a lower portion of the fin structure; etching the middle portion of the fin structure; and forming a first source/drain structure surrounding the middle portion of the fin structure.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: April 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Chih-Chieh Yeh
  • Patent number: 10964798
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes semiconductor wires disposed over a substrate, a source/drain epitaxial layer in contact with the semiconductor wires, a gate dielectric layer disposed on and wrapping around each channel region of the semiconductor wires, a gate electrode layer disposed on the gate dielectric layer and wrapping around the each channel region, and dielectric spacers disposed in recesses formed toward the source/drain epitaxial layer.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen
  • Patent number: 10957607
    Abstract: A method for manufacturing a semiconductor device is provided. A semiconductor substrate is received. The semiconductor substrate is patterned to form a plurality of protrusions spaced from one another, wherein the protrusion comprises a base section, and a seed section stacked on the base section. A plurality of first insulative structures are formed, covering sidewalls of the base sections and exposing sidewalls of the seed sections. A plurality of spacers are formed, covering the sidewalls of the seed sections. The first insulative structures are partially removed to partially expose the sidewalls of the base sections. The base sections exposed from the first insulative structures are removed. A plurality of second insulative structures are formed under the seed sections.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Wei-Sheng Yun, You-Ru Lin, Shao-Ming Yu
  • Publication number: 20210057539
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Inventors: Kuo-Cheng CHIANG, Chen-Feng HSU, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung Ying LEE, Wei-Sheng YUN, Yu-Lin YANG
  • Publication number: 20210050457
    Abstract: A method for forming a gate-all-around structure is provided. The method includes forming a plurality of a first type of semiconductor layers and a plurality of a second type of semiconductor layers alternately stacked over a fin. The first type of semiconductor layers includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has a thickness greater than that of the second semiconductor layer. The method also includes removing the second type of semiconductor layers. In addition, the method includes forming a gate to wrap around the first type of semiconductor layers.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsuan HSIAO, Wei-Sheng YUN, Winnie Victoria Wei-Ning CHEN, Tung Ying LEE, Ling-Yen YEH
  • Publication number: 20210020763
    Abstract: A device includes a semiconductor fin, a first epitaxy structure and a gate stack. The semiconductor fin protrudes from a substrate. The first epitaxy feature laterally surrounds a first portion of the semiconductor fin. The gate stack laterally surrounds a second portion of the semiconductor fin above the first portion of the semiconductor fin, wherein the second portion of the semiconductor fin has a lower surface roughness than the first epitaxy feature.
    Type: Application
    Filed: October 7, 2020
    Publication date: January 21, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Tung-Ying LEE, Chih-Chieh YEH
  • Patent number: 10886180
    Abstract: A semiconductor device and a method of manufacturing the same are disclosed. The semiconductor device includes a plurality of fins on a substrate. A fin end spacer is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. A gate electrode layer is formed on the insulating layer and wrapping around the each channel region. Sidewall spacers are formed on the gate electrode layer.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Tzu-Chung Wang, Kai-Tai Chang, Wei-Sheng Yun
  • Patent number: 10825933
    Abstract: Present disclosure provides gate-all-around structure including a semiconductor fin having a top surface, a first nanowire over the top surface, a first space between the top surface and the first nanowire, an Nth nanowire and an (N+1)th nanowire over the first nanowire, and a second space between the Nth nanowire and the (N+1)th nanowire. The first space is greater than the second space. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Hsuan Hsiao, Wei-Sheng Yun, Winnie Victoria Wei-Ning Chen, Tung Ying Lee, Ling-Yen Yeh
  • Patent number: 10818777
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Cheng Chiang, Chen-Feng Hsu, Chao-Ching Cheng, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 10811518
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 18, 2019
    Date of Patent: October 20, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 10804367
    Abstract: A semiconductor device includes a substrate; an I/O device over the substrate; and a core device over the substrate. The I/O device includes a first gate structure having an interfacial layer; a first high-k dielectric stack over the interfacial layer; and a conductive layer over and in physical contact with the first high-k dielectric stack. The core device includes a second gate structure having the interfacial layer; a second high-k dielectric stack over the interfacial layer; and the conductive layer over and in physical contact with the second high-k dielectric stack. The first high-k dielectric stack includes the second high-k dielectric stack and a third dielectric layer.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Wei-Sheng Yun, I-Sheng Chen, Shao-Ming Yu, Tzu-Chiang Chen, Chih Chieh Yeh
  • Patent number: 10804375
    Abstract: A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate. A spacer is formed on a sidewall of a first portion of the fin. An epitaxy feature is grown from a second portion of the fin that is in a position lower than the first portion of the fin, in which the forming the epitaxy feature is performed after the forming the spacer. The spacer is removed to expose the first portion of the fin. A gate stack is formed around the exposed first portion of the fin.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: October 13, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Tung-Ying Lee, Chih-Chieh Yeh
  • Patent number: 10797174
    Abstract: A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: October 6, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kai-Tai Chang, Tung Ying Lee, Wei-Sheng Yun, Tzu-Chung Wang, Chia-Cheng Ho, Ming-Shiang Lin, Tzu-Chiang Chen
  • Publication number: 20200286857
    Abstract: A method includes forming a fin structure over a semiconductor substrate; forming a liner covering the fin structure; etching back the liner to expose an upper portion of the fin structure; forming a spacer covering the upper portion of the fin structure; etching the liner to expose a middle portion of the fin structure, wherein the remaining liner covers a lower portion of the fin structure; etching the middle portion of the fin structure; and forming a first source/drain structure surrounding the middle portion of the fin structure.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Chih-Chieh YEH
  • Publication number: 20200258740
    Abstract: A semiconductor device includes a substrate, a first semiconductor stack including elongated semiconductor features isolated from each other and overlaid in a direction perpendicular to a top surface of the substrate, and a second semiconductor stack including elongated semiconductor features isolated from each other and overlaid in the direction perpendicular to the top surface of the substrate. The second semiconductor stack has different geometric characteristics than the first semiconductor stack. A top surface of the first semiconductor stack is coplanar with a top surface of the second semiconductor stack.
    Type: Application
    Filed: December 30, 2019
    Publication date: August 13, 2020
    Inventors: Tung Ying Lee, Shao-Ming Yu, Wei-Sheng Yun
  • Publication number: 20200227534
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Inventors: Kuo-Cheng CHIANG, Chen-Feng HSU, Chao-Ching CHENG, Tzu-Chiang CHEN, Tung Ying LEE, Wei-Sheng YUN, Yu-Lin YANG
  • Patent number: 10714592
    Abstract: In a method of manufacturing a semiconductor device, a fin structure, in which first semiconductor layers and second semiconductor layers are alternately stacked, is formed. A sacrificial gate structure is formed over the fin structure. A source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space. The first semiconductor layers are laterally etched through the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers. A source/drain epitaxial layer is formed in the source/drain space to cover the inner spacer. A lateral end of each of the first semiconductor layers has a V-shape cross section after the first semiconductor layers are laterally etched.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: July 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chao-Ching Cheng, Chen-Feng Hsu, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang
  • Patent number: 10665569
    Abstract: A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Chih-Chieh Yeh