Patents by Inventor Wei-Sheng Yun

Wei-Sheng Yun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190103317
    Abstract: A method of manufacturing a semiconductor device includes forming a first semiconductor layer having a first composition over a semiconductor substrate, and forming a second semiconductor layer having a second composition over the first semiconductor layer. Another first semiconductor layer having the first composition is formed over the second semiconductor layer. A third semiconductor layer having a third composition is formed over the another first semiconductor layer. The first semiconductor layers, second semiconductor layer, and third semiconductor layer are patterned to form a fin structure. A portion of the third semiconductor layer is removed thereby forming a nanowire comprising the second semiconductor layer, and a conductive material is formed surrounding the nanowire. The first semiconductor layers, second semiconductor layer, and third semiconductor layer include different materials.
    Type: Application
    Filed: March 29, 2018
    Publication date: April 4, 2019
    Inventors: Shao-Ming YU, Tung Ying LEE, Wei-Sheng YUN, Fu-Hsiang YANG
  • Publication number: 20190067452
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes providing a substrate having a base portion and a fin portion over the base portion. The fin portion has a channel region and a source/drain region. The method also includes forming a stack structure over the fin portion. The stack structure includes first and second semiconductor layers. The method also includes forming a source/drain portion in the stack structure at the source/drain region, and removing a portion of the second semiconductor layer in the channel region in an etching process. The remaining portion of the first semiconductor layer in the channel region forms a nanowire. The method further includes forming a gate dielectric layer surrounding the nanowire, forming a high-k dielectric layer surrounding the gate dielectric layer, and forming a gate electrode surrounding the high-k dielectric layer.
    Type: Application
    Filed: August 31, 2017
    Publication date: February 28, 2019
    Inventors: Chao-Ching CHENG, Wei-Sheng YUN, Shao-Ming YU, Tsung-Lin LEE, Chih-Chieh YEH
  • Publication number: 20190019888
    Abstract: A vertical transistor device and a method for fabricating the same are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and fin portions located on the bottom portion. Each of the fin portions includes an upper portion and a lower portion. The lower portion is located between the bottom portion of the semiconductor substrate and the upper portion, in which the lower portion includes recesses. The first sources/drains are disposed on terminals of the upper portions of the fin portions. The second sources/drains are disposed on the recesses of the lower portions of the fin portions, in which the sources/drains are not merged with each other. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the recesses on the lower portions of the fin portions.
    Type: Application
    Filed: July 14, 2017
    Publication date: January 17, 2019
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Chih-Chieh YEH
  • Patent number: 10181524
    Abstract: A vertical transistor device and a method for fabricating the same are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and fin portions located on the bottom portion. Each of the fin portions includes an upper portion and a lower portion. The lower portion is located between the bottom portion of the semiconductor substrate and the upper portion, in which the lower portion includes recesses. The first sources/drains are disposed on terminals of the upper portions of the fin portions. The second sources/drains are disposed on the recesses of the lower portions of the fin portions, in which the sources/drains are not merged with each other. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the recesses on the lower portions of the fin portions.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: January 15, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Sheng Yun, Shao-Ming Yu, Chih-Chieh Yeh
  • Publication number: 20180342480
    Abstract: A vertical transistor device and its fabrication method are provided. The vertical transistor device includes a semiconductor substrate, first sources/drains and second sources/drains. The semiconductor substrate includes a bottom portion and a fin portion. The fin portion is located on the bottom portion. The fin portion includes an upper portion and a lower portion located between the bottom portion of the semiconductor substrate and the upper portion. The lower portion includes a narrow portion having a width smaller than a width of the upper portion, and the narrow portion contacts an interface portion of the upper portion. The sources/drains are disposed on the on the narrow portion of the lower portion of the fin portion. In the method for fabricating the vertical transistor device, the lower portions of the fin portions are patterned to form the narrow portions where the sources are disposed.
    Type: Application
    Filed: October 26, 2017
    Publication date: November 29, 2018
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Chih-Chieh YEH
  • Publication number: 20180277658
    Abstract: A method for manufacturing a semiconductor device is provided by follows. A fin is formed over a substrate. A spacer is formed on a sidewall of a first portion of the fin. An epitaxy feature is grown from a second portion of the fin that is in a position lower than the first portion of the fin, in which the forming the epitaxy feature is performed after the forming the spacer. The spacer is removed to expose the first portion of the fin. A gate stack is formed around the exposed first portion of the fin.
    Type: Application
    Filed: June 23, 2017
    Publication date: September 27, 2018
    Inventors: Wei-Sheng YUN, Shao-Ming YU, Tung-Ying LEE, Chih-Chieh YEH
  • Patent number: 8809202
    Abstract: Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Weng, Wei-Sheng Yun, Shao-Ming Yu, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann
  • Publication number: 20130210212
    Abstract: Methods of manufacturing semiconductor devices are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes providing a workpiece, and forming a protective material over a bottom surface and edges of the workpiece. A top surface of the workpiece is processed. The protective material protects the edges and the bottom surface of the workpiece during the processing of the top surface of the workpiece.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 15, 2013
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Weng, Wei-Sheng Yun, Shao-Ming Yu, Hsin-Chih Chen, Chih-Hsin Ko, Clement Hsingjen Wann