Patents by Inventor Wei-Shun Wang

Wei-Shun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11009882
    Abstract: The disclosure is related to a method and a system for obstacle detection adapted to a self-guiding machine. The method is performed in the system including a controller for driving the system, a light emitter, a light sensor, an image processor and a central processor. The light emitter and the light sensor are set apart at a distance. When the light emitter emits an indicator light being projected onto a path the self-guiding machine travels toward, the light sensor senses the indicator light. An image containing the indicator light is generated. After analyzing the image, at least one feature of the indicator light being sensed can be obtained and used to obtain a spatial relationship between the self-guiding machine and an obstacle. The spatial relationship allows the system to determine if the self-guiding machine will collide with a wall or fall from a cliff.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 18, 2021
    Assignee: PIXART IMAGING INC.
    Inventors: Kai-Shun Chen, Wei-Chung Wang
  • Publication number: 20210050322
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Applicant: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Publication number: 20210035948
    Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
    Type: Application
    Filed: August 21, 2020
    Publication date: February 4, 2021
    Applicant: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 10833044
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: November 10, 2020
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Patent number: 10756049
    Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: August 25, 2020
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Publication number: 20200168579
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Application
    Filed: January 31, 2020
    Publication date: May 28, 2020
    Applicant: Tessera, Inc.
    Inventors: Hiroaki SATO, Teck-Gyu KANG, Belgacem HABA, Philip R. OSBORN, Wei-Shun WANG, Ellis CHAU, Ilyas MOHAMMED, Norihito MASUDA, Kazuo SAKUMA, Kiyoaki HASHIMOTO, Kurosawa INETARO, Tomoyuki KIKUCHI
  • Patent number: 10593643
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: March 17, 2020
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Patent number: 10163808
    Abstract: A module includes a circuit package and a top external shield layer. The circuit package includes multiple electronic components on a substrate; at least one side shield structure located at a corresponding at least one side edge region of the circuit package and electrically connected to ground, the at least one side shield structure being positioned on the substrate or on a pad on the substrate; and a molded compound disposed over the substrate, the electronic components, and the at least one side shield structure. The top external shield layer is disposed on a top outer surface of the circuit package and is electrically connected to ground. The at least one side shield structure and the top external shield layer provide an external shield of the module configured to protect the circuit package from external electromagnetic radiation and environmental stress.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: December 25, 2018
    Assignee: Avago Technologies International Sales Pte. Limited
    Inventors: Nitesh Kumbhat, Deog Soon Choi, Wei-Shun Wang
  • Publication number: 20180350766
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Application
    Filed: August 8, 2018
    Publication date: December 6, 2018
    Applicant: Tessera, Inc.
    Inventors: Hiroaki SATO, Teck-Gyu KANG, Belgacem HABA, Philip R. OSBORN, Wei-Shun WANG, Ellis CHAU, Ilyas MOHAMMED, Norihito MASUDA, Kazuo SAKUMA, Kiyoaki HASHIMOTO, Kurasawa INETARO, Tomoyuki KIKUCHI
  • Patent number: 10062661
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: August 28, 2018
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Publication number: 20180026007
    Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
    Type: Application
    Filed: September 8, 2017
    Publication date: January 25, 2018
    Applicant: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 9865479
    Abstract: A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: January 9, 2018
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Wei-Shun Wang, Li Sun, Ashish Alawani, Lea-Teng Lee
  • Publication number: 20170309593
    Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.
    Type: Application
    Filed: July 7, 2017
    Publication date: October 26, 2017
    Inventors: Teck-Gyu KANG, Wei-Shun WANG, Hiroaki SATO, Kiyoaki HASHIMOTO, Yoshikuni NAKADAIRA, Norihito MASUDA, Belgacem HABA, Ilyas MOHAMMED, Philip DAMBERG
  • Publication number: 20170301559
    Abstract: A method is provided for attaching components to pads on a PCB, where total accumulated tolerances are reduced by separating accumulated tolerances into multiple processes. The method includes performing first and second processes having first and second accumulated tolerances, respectively. The first process includes placing a first stencil over the PCB, the first stencil defining first apertures corresponding to the pads; printing solder paste onto the pads using the first stencil; and reflowing the printed solder paste to form corresponding solder bumps on the pads. The second process includes placing a second stencil over the PCB, the second stencil defining second apertures corresponding to the pads; printing flux onto the solder bumps using the second stencil; placing at least one component on the printed flux; and reflowing the printed flux and the solder bumps to form corresponding solder joints between the at least one component and the first pads, respectively.
    Type: Application
    Filed: April 15, 2016
    Publication date: October 19, 2017
    Inventors: Wei-Shun Wang, Li Sun, Ashish Alawani, Lea-Teng Lee
  • Publication number: 20170287733
    Abstract: Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.
    Type: Application
    Filed: June 21, 2017
    Publication date: October 5, 2017
    Inventors: Hiroaki SATO, Teck-Gyu KANG, Belgacem HABA, Philip R. OSBORN, Wei-Shun WANG, Ellis CHAU, Ilyas MOHAMMED, Norihito MASUDA, Kazuo SAKUMA, Kiyoaki HASHIMOTO, Kurosawa INETARO, Tomoyuki KIKUCHI
  • Patent number: 9761558
    Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: September 12, 2017
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 9716075
    Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.
    Type: Grant
    Filed: September 11, 2015
    Date of Patent: July 25, 2017
    Assignee: Tessera, Inc.
    Inventors: Teck-Gyu Kang, Wei-Shun Wang, Hiroaki Sato, Kiyoaki Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
  • Patent number: 9691731
    Abstract: A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: June 27, 2017
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Publication number: 20170118875
    Abstract: A module includes a circuit package and a top external shield layer. The circuit package includes multiple electronic components on a substrate; at least one side shield structure located at a corresponding at least one side edge region of the circuit package and electrically connected to ground, the at least one side shield structure being positioned on the substrate or on a pad on the substrate; and a molded compound disposed over the substrate, the electronic components, and the at least one side shield structure. The top external shield layer is disposed on a top outer surface of the circuit package and is electrically connected to ground. The at least one side shield structure and the top external shield layer provide an external shield of the module configured to protect the circuit package from external electromagnetic radiation and environmental stress.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventors: Nitesh Kumbhat, Deog Soon Choi, Wei-Shun Wang
  • Publication number: 20160211237
    Abstract: A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.
    Type: Application
    Filed: December 22, 2015
    Publication date: July 21, 2016
    Inventors: Hiroaki Sato, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi