Patents by Inventor Wei-Shun Wang

Wei-Shun Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8299626
    Abstract: A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: October 30, 2012
    Assignee: Tessera, Inc.
    Inventors: Ilyas Mohammed, Belgacem Haba, Sean Moran, Wei-Shun Wang, Ellis Chau, Christopher Wade
  • Publication number: 20120155055
    Abstract: A microelectronic assembly may include a substrate including a rigid dielectric layer having electrically conductive elements, a microelectronic element having a plurality of contacts exposed at a face thereof, and conductive vias extending through a compliant dielectric layer overlying the rigid dielectric layer. The vias electrically connect the substrate contacts respectively to the conductive elements, and the substrate contacts are joined respectively to the contacts of the microelectronic element. The vias, compliant layer and substrate contacts are adapted to appreciably relieve stress at the substrate contacts associated with differential thermal contact and expansion of the assembly.
    Type: Application
    Filed: June 10, 2011
    Publication date: June 21, 2012
    Applicant: Tessera, Inc.
    Inventors: Teck-Gyu Kang, Wei-Shun Wang, Hiroaki Sato, Kiyoaki Hashimoto, Yoshikuni Nakadaira, Norihito Masuda, Belgacem Haba, Ilyas Mohammed, Philip Damberg
  • Publication number: 20090045524
    Abstract: A microelectronic package includes a lower unit having a lower unit substrate with conductive features and a top and bottom surface. The lower unit includes one or more lower unit chips overly/ing the top surface of the lower unit substrate that are electrically connected to the conductive features of the lower unit substrate. The microelectronic package also includes an upper unit including an upper unit substrate having conductive features, top and bottom surfaces and a hole extending between such top and bottom surfaces. The upper unit further includes one or more upper unit chips overlying the top surface of the upper unit substrate and electrically connected to the conductive features of the upper unit substrate by connections extending within the hole. The upper unit may include an upper unit encapsulant that covers the connections of the upper unit and the one or more upper unit chips.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 19, 2009
    Applicant: Tessera, Inc.
    Inventors: IIyas Mohammed, Belgacem Haba, Sean Moran, Wei-Shun Wang, Ellis Chau, Christopher Wade