Abstract: The invention provides a phase change memory device comprising a stacked structure disposed on a substrate. The stacked structure comprises a first electrode, a second electrode overlying the first electrode and an insulating layer interposed between the first and the second electrodes. A memory spacer is formed on part of the sidewall of the stacked structure to contact the first electrode, the insulating layer and the second electrode.

Abstract: A phase change memory (PCM) device includes a substrate, bottom electrodes disposed in the substrate, a first dielectric layer disposed on the substrate, second dielectric layers, third dielectric layers, cup-shaped thermal electrodes, top electrodes, and PC material spacers. In the PCM device, each cup-shaped thermal electrode contacts with each bottom electrode. Second and third dielectric layers are disposed over the substrate in different directions, wherein each of the second and third dielectric layers covers a portion of the area surrounded by each cup-shaped thermal electrode, and the third dielectric layers overlay the second dielectric layers. The top electrodes are disposed on the third dielectric layers, wherein a plurality of stacked structure composed of the third dielectric layers and the top electrodes are formed thereon.

Abstract: A phase change memory device and fabricating method are provided. A disk-shaped phase change layer is buried within the insulating material. A center via and ring via are formed by a lithography. The center via is located in the center of the phase change layer and passes through the phase change layer, and the ring via takes the center via as a center. A heating electrode within the center via performs Joule heating of the phase change layer, and the contact area between the phase change layer and the heating electrode is reduced by controlling the thickness of the phase change layer. Furthermore, a second electrode within the ring via dissipates the heat transmitted to the contact interface between the phase change layers, so as to avoid transmitting the heat to the etching boundary at the periphery of the phase change layer.

Abstract: A phase-change memory layer and method for manufacturing the same and a phase-change memory cell are provided. The phase-change memory layer is crystallized by adding one or more heterogeneous crystals that do not react with phase-change materials as the crystal nucleus, so as to reduce the time for transforming to the crystalline state from the amorphous state.

Abstract: A phase change memory (PCM) cell and fabricating method thereof are provided. A phase change layer is etched into a tapered structure, and then a dielectric layer on the phase change layer is planarized, until a tip of the tapered structure is exposed for contacting a heating electrode. Therefore, when the area of the exposed tip of the phase change layer is controlled to be of an extremely small size, the contact area between the phase change layer and the heating electrode is reduced; thereby the operation current is lowered.

Abstract: A lateral phase change memory with spacer electrodes and method of manufacturing the same are provided. The memory is formed by connecting the conductive electrodes with lower resistivity and the spacer electrodes with higher resistivity, and filling the phase change material between the spacer electrodes. Therefore, the area that the phase change material contacts the spacer electrodes and the volume of the phase change material can be reduced; thereby the programming current and power consumption of the phase change memory are reduced.

Abstract: An organic bistable memory device has an organic layer with two sides, each having a dielectric layer with an electrode. When voltage is applied to the two electrodes, the memory may be switched and operated between a high impedance state and a low impedance state. This reduces negative effects on the memory device due to poor quality material or non-uniform manufacturing of the device, effects such as reduced on/off current ratio, shortened retention time and shorting failure in the device. Also, the disclosed organic bistable memory provides evidence to improve our understanding of bistable memory.

Abstract: A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.

Abstract: An organic light emitting diode (OLED) device comprises a substrate, an anode layer, a luminescence layer, a hole blocking layer and a cathode layer. The anode layer is disposed on the substrate; the luminescence layer is disposed on the anode layer; the hole blocking layer is disposed on the luminescence layer; the cathode layer is disposed on the hole blocking layer. In addition the luminescence layer comprises a hole transporting material and a phosphorescent material, wherein the weight percentage of the bole transporting material and the phosphorescent material is between 40%˜60%.

Abstract: An organic light emitting diode (OLED) device that comprises a substrate, an anode layer, a light-emitting layer, a hole blocking layer and a cathode layer. The anode layer is positioned over the substrate and the light-emitting layer is positioned over the anode layer. The hole blocking layer is positioned over the light-emitting layer and the cathode layer is positioned over the hole blocking layer. The light-emitting layer is an organic material layer consisted of hole transporting material and phosphorescent material and that the concentration of hole transporting material and phosphorescent material in the organic material layer is between 40% to 60% by weight.

Abstract: Within both a micro fabrication and a method for fabricating the micro fabrication there is formed over a substrate a spirally patterned conductor layer spirally topographically tapered in a vortex shape. The spirally patterned conductor layer is particularly useful as a microelectronic inductor structure within a microelectronic fabrication.

Abstract: A vertical nanotube transistor and a process for fabricating the same. First, a source layer and a catalyst layer are successively formed on a substrate. A dielectric layer is formed on the catalyst layer and the substrate. Next, the dielectric layer is selectively removed to form a first dielectric mesa, a gate dielectric layer spaced apart from the first dielectric mesa by a first opening, and a second dielectric mesa spaced apart from the gate dielectric layer by a second opening. Next, a nanotube layer is formed in the first opening. Finally, a drain layer is formed on the nanotube layer and the first dielectric mesa, and a gate layer is formed in the second opening. The formation position of the nanotubes can be precisely controlled.

Abstract: Within both a micro fabrication and a method for fabricating the micro fabrication there is formed over a substrate a spirally patterned conductor layer spirally topographically tapered in a vortex shape. The spirally patterned conductor layer is particularly useful as a microelectronic inductor structure within a microelectronic fabrication.