Patents by Inventor Wei-The Chen

Wei-The Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • PIXEL ARRAY SUBSTRATE
    Publication number: 20170194505
    Abstract: A pixel array substrate including a substrate having at least one via, at least one conductor disposed in the at least one via, pixel units, scan lines electrically connected to the pixel units, at least one shift register and at least one bus line is provided. The pixel units, the scan lines and the at least one shift register are disposed on a first surface of the substrate. The at least one shift register is used to transmit a first gate signal to the corresponding scan lines. The at least one bus line is disposed on a second surface of the substrate. The at least one bus line is electrically connected to the at least one shift register by the at least one conductor.
    Type: Application
    Filed: January 3, 2017
    Publication date: July 6, 2017
    Applicant: Au Optronics Corporation
    Inventors: Wei-Min Cho, Yu-Sheng Huang, Chia-Wei Chen
  • Hydrophilic film, preparation method and applications thereof
    Patent number: 9696318
    Abstract: The present invention provides a hydrophilic film that causes a liquid to diffuse rapidly in a single direction. The hydrophilic film comprises a substrate having a texture of parallel sunken and raised patterns, and a hydrophilic coat comprising a coat of silicon dioxide particles. The present invention also provides a method for preparing the hydrophilic film. The method comprises: preparing an aqueous dispersion of silicon dioxide particles, wherein the average size of the silicon dioxide particles is 1 to 60 nm, and the concentration of the silicon dioxide particles is 0.05% to 15% by weight; coating the aqueous dispersion of silicon dioxide particles on a substrate, wherein the substrate has a texture of parallel sunken and raised patterns; and drying the substrate coated with the aqueous dispersion of silicon dioxide particles.
    Type: Grant
    Filed: September 12, 2013
    Date of Patent: July 4, 2017
    Assignee: 3M Innovative Properties Company
    Inventors: Te-Wei Chen, Huang Chin Hung, Naiyong Jing
  • Method and apparatus for connecting packages onto printed circuit boards
    Patent number: 9698118
    Abstract: Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Hsien-Wei Chen
  • Dummy gate technology to avoid shorting circuit
    Patent number: 9698047
    Abstract: Semiconductor devices and method of manufacturing such semiconductor devices are provided for improved FinFET memory cells to avoid electric short often happened between metal contacts of a bit cell, where the meal contacts are positioned next to a dummy gate of a neighboring dummy edge cell. In one embodiment, during the patterning of a gate layer on a substrate surface, an improved gate slot pattern is used to extend the lengths of one or more gate slots adjacent bit lines so as to pattern and sectionalize a dummy gate line disposed next to metal contacts of an active memory cell. In another embodiment, during the patterning of gate lines, the distances between one or more dummy gates lines disposed adjacent an active memory cell are adjusted such that their locations within dummy edge cells are shifted in position to be away from metal contacts of the active memory cell.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: July 4, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Chih-Sen Huang, Shih-Fang Tzou, Yi-Wei Chen, Yung-Feng Cheng, Li-Ping Huang, Chun-Hsien Huang, Chia-Wei Huang, Yu-Tse Kuo
  • Opening in the Pad for Bonding Integrated Passive Device in InFO Package
    Publication number: 20170188458
    Abstract: A package includes a conductive pad, with a plurality of openings penetrating through the conductive pad. A dielectric layer encircles the conductive pad. The dielectric layer has portions filling the plurality of openings. An Under-Bump Metallurgy (UBM) includes a via portion extending into the dielectric layer to contact the conductive pad. A solder region is overlying and contacting the UBM. An integrated passive device is bonded to the UBM through the solder region.
    Type: Application
    Filed: December 28, 2015
    Publication date: June 29, 2017
    Inventors: Cheng-Hsien Hsieh, Chi-Hsi Wu, Chen-Hua Yu, Der-Chyang Yeh, Hsien-Wei Chen, Li-Han Hsu, Wei-Cheng Wu
  • Sensor and Method for Fabricating the Same
    Publication number: 20170186886
    Abstract: A sensor includes a first reception unit configured for sensing a first signal of a first frequency band and a second reception unit configured for sensing a second signal of a second frequency band. There is a height difference between the first reception unit and the second reception unit.
    Type: Application
    Filed: July 28, 2016
    Publication date: June 29, 2017
    Inventors: Huan-Hsiang Weng, Feng-Jung Hsu, Chu-Yuan Yang, Chih-Wei Chen, Yi-Hua Chang
  • CHIP AND ELECTRONIC DEVICE
    Publication number: 20170187183
    Abstract: The present invention provides a chip and an electronic device. The chip comprises at least one pin, and the chip comprises at least one ESD (Electrostatic Discharge) protection circuit inside, and the ESD protection circuit is employed to reduce or eliminate a damage of electrostatic to other elements or circuit inside the chip, and the ESD protection circuit is located corresponding to a pin, and the ESD protection circuit is electrically coupled to the pin. The electronic device comprises the aforesaid chip.
    Type: Application
    Filed: December 8, 2015
    Publication date: June 29, 2017
    Applicant: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Xianming ZHANG, Yu-Yeh CHEN, Ming-wei CHEN, Dan CAO
  • NOVEL COPPER-CYSTEAMINE AND METHODS OF USE
    Publication number: 20170182166
    Abstract: Structure and luminescence properties of a new Cu-Cyteamine (Cu-Cy) crystal material are provided. The crystal structure of the Cu-Cy is determined by single crystal X-ray diffraction. It is found that the compound crystallizes in the monoclinic space group C2/c and cell parameters are a=7.5510(4) ?, b=16.9848(7) ?, c=7.8364(4) ?, ?=104.798(3)°. The new Cu-Cy crystal material of the invention is also useful for treatment of cancer.
    Type: Application
    Filed: January 31, 2017
    Publication date: June 29, 2017
    Inventors: Wei Chen, Lun Ma
  • Structure for Die Probing
    Publication number: 20170186655
    Abstract: A package includes a device die, which includes a metal pillar at a top surface of the device die, and a solder region on a sidewall of the metal pillar. A molding material encircles the device die, wherein a top surface of the molding material is substantially level with a top surface of the device die. A dielectric layer overlaps the molding material and the device die, with a bottom surface of the dielectric layer contacting a top surface of the device die and a top surface of the molding material. A redistribution line (RDL) extends into the dielectric layer to electrically couple to the metal pillar.
    Type: Application
    Filed: March 10, 2017
    Publication date: June 29, 2017
    Inventor: Hsien-Wei Chen
  • SYSTEM AND METHOD FOR AN IMPROVED INTERCONNECT STRUCTURE
    Publication number: 20170186713
    Abstract: Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer including a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 ?m.
    Type: Application
    Filed: March 16, 2017
    Publication date: June 29, 2017
    Inventors: Hsien-Wei Chen, Hao-Yi Tsai, Mirng-Ji Lii, Chen-Hua Yu, Tsung-Yuan Yu
  • LAMP
    Publication number: 20170184771
    Abstract: A light guide element and a lamp are provided. The light guide element includes a light-incident surface, a light-emitting surface, an outer surface and an inner surface. The light-incident surface has a first outer peripheral edge and a first inner peripheral edge. The light-emitting surface is opposite to the light-incident surface and has a second outer peripheral edge and a second inner peripheral edge. The outer surface connects the first outer peripheral edge and the second outer peripheral edge. The inner surface connects the first inner peripheral edge and the second inner peripheral edge. A first opening defined by the inner surface adjacent to the first inner peripheral edge is larger than a second opening defined by the inner surface adjacent to the second inner peripheral edge.
    Type: Application
    Filed: February 2, 2017
    Publication date: June 29, 2017
    Inventors: Wei-Chen LIN, Che-Wei CHANG
  • Miniaturized SMD diode package and process for producing the same
    Patent number: 9691735
    Abstract: A miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from a process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: June 27, 2017
    Assignee: SFI ELECTRONICS TECHNOLOGY INC.
    Inventors: Ching-Hohn Lien, Xing-Xiang Huang, Hsing-Tsai Huang, Hong-Zong Xu, Yi-Wei Chen
  • Methods and compositions for brazing, and earth-boring tools formed from such methods and compositions
    Patent number: 9687940
    Abstract: A method includes disposing a braze material between a first body and a second body. The braze material includes a first composition and a second composition. The second composition has a melting point higher than the first composition. The method also includes heating the braze material to a brazing temperature between the melting points of the first and second materials and maintaining the braze material at the brazing temperature for a period of time to transform a transient liquid phase to a solid phase, forming a bond between the first body and the second body. A braze material for securing solid bodies includes a first composition and a second composition. The first composition includes at least one element selected from the group consisting of indium, tin, zinc, and magnesium. An earth-boring tool includes a first body, a second body, and a braze material bonding the second body to the first body.
    Type: Grant
    Filed: November 18, 2014
    Date of Patent: June 27, 2017
    Assignee: Baker Hughes Incorporated
    Inventors: Wei Chen, James L. Overstreet, John H. Stevens
  • Semiconductor device
    Patent number: 9691901
    Abstract: A semiconductor device includes a substrate, a gate structure, a sidewall spacer, and an epitaxial layer. The gate structure is disposed on the substrate, and the substrate has at least one recess disposed adjacent to the gate structure. The sidewall spacer is disposed on at least two sides of the gate structure. The sidewall spacer includes a first spacer layer and a second spacer layer, and the first spacer layer is disposed between the gate structure and the second spacer layer. The epitaxial layer is disposed in the recess, and the recess is a circular shaped recess. A distance between an upmost part of the recess and the gate structure is less than a width of the sidewall spacer.
    Type: Grant
    Filed: October 2, 2015
    Date of Patent: June 27, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Wen-Jiun Shen, Chia-Jong Liu, Chung-Fu Chang, Yen-Liang Wu, Man-Ling Lu, I-Fan Chang, Yi-Wei Chen
  • Methods for forming fan-out package structure
    Patent number: 9691726
    Abstract: A method includes forming a first composite wafer including molding a plurality of device dies and a plurality of through-vias in a first molding material, and forming redistribution lines on opposite sides of the first molding material. The redistribution lines are inter-coupled through the plurality of through-vias. The method further includes forming a second composite wafer including stacking a plurality of dies to form a plurality of die stacks, and molding the plurality of die stacks in a second molding material. The second molding material fills gaps between the plurality of die stacks. The first composite wafer is bonded to the second composite wafer to form a third composite wafer.
    Type: Grant
    Filed: July 8, 2014
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Da Cheng, Hsien-Wei Chen, Cheng-Lin Huang, Meng-Tse Chen, Chung-Shi Liu
  • Ph-sensitive peptides and their nanoparticles for drug delivery
    Patent number: 9687563
    Abstract: A new nanoscale carrier made by one or more pH-sensitive peptides is provided for delivery of a biologically active substance. The peptides are composed of pH-sensitive hydrophilic and hydrophobic amino acids in the backbone. As the pH environment changes from physiological pH level to a weakly acidic environment such as near a tumor site (pH˜6.5-6.9), the peptides may dissolve, releasing the biological substance. Also provided are the delivery methods and related kits.
    Type: Grant
    Filed: August 13, 2014
    Date of Patent: June 27, 2017
    Assignee: The Trustees Of The University Of Pennsylvania
    Inventors: I-Wei Chen, Hoon Choi, Rong Zhou
  • Miniaturized SMD diode package and process for producing the same
    Patent number: 9691736
    Abstract: A process for producing a miniaturized SMD diode package involves using a diode chip whose bottom surface has a positive electrode and a negative electrode, using a circuit board instead of a conventional lead frame during packaging, and using Charge-Coupled Device (CCD) image registration technology to perform chip bonding; the beneficial advantages brought from the process for producing the same including to simplify producing process and reduce manufacturing cost, to improve accuracy and precision of producing the miniaturized SMD diode package due to using a circuit board instead of conventionally used lead frame, and to ensure the produced miniaturized SMD diode package possesses excellent diode characteristics without distortion or defect.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: June 27, 2017
    Assignee: SFI ELECTRONICS TECHNOLOGY INC.
    Inventors: Ching-Hohn Lien, Xing-Xiang Huang, Hsing-Tsai Huang, Hong-Zong Xu, Yi-Wei Chen
  • Contact Pad for Semiconductor Devices
    Publication number: 20170179051
    Abstract: Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer and/or polymer layer disposed over the substrate and a portion of the contact pad. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to an exposed portion of the contact pad. A PPI pad is disposed over the passivation layer. A transition element is disposed over the passivation layer and is coupled between the PPI line and the PPI pad. The transition element includes line having a width greater than the PPI line.
    Type: Application
    Filed: March 3, 2017
    Publication date: June 22, 2017
    Inventors: Jie Chen, Hsien-Wei Chen, Ying-Ju Chen
  • ELECTRONIC SYSTEM AND NON- TRANSITORY COMPUTER READABLE RECORDING MEDIUM CAN PERFORM REPORT RATE SETTING METHOD
    Publication number: 20170177510
    Abstract: An electronic system that can automatically set a report rate, which comprises: a first electronic apparatus; a second electronic apparatus; a transmitting interface, wherein the second electronic apparatus transmits data to the first electronic apparatus via the transmitting interface; and a processing unit, for automatically setting a report rate of the second electronic apparatus or the transmitting interface according to a type of a software program that the first electronic apparatus executes. The type of the software program can be replaced by other factors.
    Type: Application
    Filed: March 2, 2017
    Publication date: June 22, 2017
    Inventor: Chun-Wei Chen
  • METHODS OF MODIFYING SEARCH AREAS
    Publication number: 20170180754
    Abstract: Methods and systems for evaluating a search area for encoding video are provided. The method comprises receiving video captured by an image capture device, the video comprising video frame components. Additionally, the method comprises receiving optical flow field data associated with the video frame component, wherein at least a portion of the optical flow field data is captured by sensors. The method also comprises determining a search area based on the optical flow field data.
    Type: Application
    Filed: March 7, 2017
    Publication date: June 22, 2017
    Inventors: Yannan Wu, Xiaozheng Tang, Wei Chen, Zisheng Cao, Mingyu Wang