Patents by Inventor Wei-The Chen

Wei-The Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Discrete Polymer in Fan-Out Packages
    Publication number: 20170154870
    Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Hsien-Wei Chen, Jie Chen
  • Methods of Forming Connector Pad Structures, Interconnect Structures, and Structures Thereof
    Publication number: 20170154862
    Abstract: Methods of forming connector pad structures, interconnect structures, and structures thereof are disclosed. In some embodiments, a method of forming a connector pad structure includes forming an underball metallization (UBM) pad, and increasing a surface roughness of the UBM pad by exposing the UBM pad to a plasma treatment. A polymer material is formed over a first portion of the UBM pad, leaving a second portion of the UBM pad exposed.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Chia-Lun Chang, Chung-Shi Liu, Hsiu-Jen Lin, Hsien-Wei Chen, Ming-Da Cheng, Wei-Yu Chen
  • Discrete polymer in fan-out packages
    Patent number: 9666502
    Abstract: A package includes a first molding material, a lower-level device die in the first molding material, a dielectric layer over the lower-level device die and the first molding material, and a plurality of redistribution lines extending into the first dielectric layer to electrically couple to the lower-level device die. The package further includes an upper-level device die over the dielectric layer, and a second molding material molding the upper-level device die therein. A bottom surface of a portion of the second molding material contacts a top surface of the first molding material.
    Type: Grant
    Filed: April 17, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsien-Wei Chen, Jie Chen
  • Semiconductor device having field plate disposed on isolation feature and method for forming the same
    Patent number: 9666699
    Abstract: The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: May 30, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Pei-Heng Hung, Manoj Kumar, Hsiung-Shih Chang, Chia-Hao Lee, Jun-Wei Chen
  • Touch input determining method which can determine if the touch input is valid or not valid and electronic apparatus applying the method
    Patent number: 9665162
    Abstract: A touch input determining method applied to an electronic apparatus with a touch sensing device, which comprises: (a) determining a size for a region of the touch sensing device that an object provides at least one touch input to; (b) if the size is larger than or equals to a first predetermined value, not determining the touch input is a valid touch input; and (c) if the size is smaller than or equals to a second predetermined value, not determining the touch input is a valid touch input, wherein the second predetermined value is smaller than the first predetermined value.
    Type: Grant
    Filed: January 26, 2015
    Date of Patent: May 30, 2017
    Assignee: HTC Corporation
    Inventors: Hsin-Ti Chueh, Chia-Wei Chen, Ssu-Po Chin, Abhishek Saxena, Sheng-Yang Pan, Chien-Lung Chou, Chun-Hao Fan
  • Alignment mark design for packages
    Patent number: 9666522
    Abstract: A package includes a device die, a molding material molding the device die therein, a through-via penetrating through the molding material, and an alignment mark penetrating through the molding material. A redistribution line is on a side of the molding material. The redistribution line is electrically coupled to the through-via.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Li-Hsien Huang, Hsien-Wei Chen, Ching-Wen Hsiao, Der-Chyang Yeh, Shin-Puu Jeng, Chen-Hua Yu
  • PACKING MATERIAL AND PACKAGE BOX
    Publication number: 20170144815
    Abstract: A package box includes a substrate board and a plurality of projections. The projections are formed on the substrate board. The substrate board includes a first surface and a second surface. The first surface is opposite to the second surface. Each of the projections is formed when the first surface of the substrate board protrudes toward the second surface of the substrate board.
    Type: Application
    Filed: December 18, 2015
    Publication date: May 25, 2017
    Inventors: YU-CHING LIU, XI-HANG LI, ER-WEI CHEN, BING LIU, DONG-YA WANG, CUI-LING LI
  • TOUCH SCREEN LIQUID CRYSTAL DISPLAY
    Publication number: 20170147119
    Abstract: Disclosed herein are liquid-crystal display (LCD) touch screens that integrate the touch sensing elements with the display circuitry. The integration may take a variety of forms. Touch sensing elements can be completely implemented within the LCD stackup but outside the not between the color filter plate and the array plate. Alternatively, some touch sensing elements can be between the color filter and array plates with other touch sensing elements not between the plates. In another alternative, all touch sensing elements can be between the color filter and array plates. The latter alternative can include both conventional and in-plane-switching (IPS) LCDs. In some forms, one or more display structures can also have a touch sensing function. Techniques for manufacturing and operating such displays, as well as various devices embodying such displays are also disclosed.
    Type: Application
    Filed: February 3, 2017
    Publication date: May 25, 2017
    Inventors: Steve Porter HOTELLING, Wei CHEN, Christoph H. KRAH, John Greer ELIAS, Wei Hsin YAO, John Z. ZHONG, Andrew Bert HODGE, Brian R. LAND, Willem den BOER
  • INTEGRATED CIRCUIT PACKAGES AND METHODS OF FORMING SAME
    Publication number: 20170148768
    Abstract: Packages and methods of manufacture thereof are described. A package may include a first package and a die structure disposed over the first package. The first package may include: a first encapsulant; a first via structure within the first encapsulant; a first die within the first encapsulant, at least a portion of the first encapsulant being interposed between a sidewall of the first die and a sidewall of the first via structure; a second die within the first encapsulant, an active side of the second die facing an active side of the first die; and a first via chip within the first encapsulant, the first via chip comprising one or more through vias, wherein the first via chip is disposed at the active side of the first die, and between the second die and the first via structure.
    Type: Application
    Filed: February 6, 2017
    Publication date: May 25, 2017
    Inventors: An-Jhih Su, Hsien-Wei Chen
  • Methods and apparatus of packaging semiconductor devices
    Patent number: 9659890
    Abstract: Methods and apparatuses for wafer level packaging (WLP) semiconductor devices are disclosed. A redistribution layer (RDL) is formed on a first passivation layer in contact with a conductive pad over a surface of a die. The RDL layer is on top of a first region of the first passivation layer. A second passivation layer is formed on the RDL layer with an opening to expose the RDL layer, and over the first passivation layer. An under bump metallization (UBM) layer is formed over the second passivation layer in contact with the exposed RDL layer. A second region of the first passivation layer disjoint from the first region is determined by projecting an outer periphery of a solder ball or other connector onto the surface.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Wei Tu, Yian-Liang Kuo, Tsung-Fu Tsai, Ru-Ying Huang, Ming-Song Sheu, Hsien-Wei Chen
  • Antenna system and a communication device
    Patent number: 9660335
    Abstract: An antenna system includes a monopole antenna with a first end connected to a feed point on a printed circuit board (PCB) and a second end being electrically floating; and a matching conductive stub with a first end connected to a ground point on the PCB and a second end being electrically floating.
    Type: Grant
    Filed: August 13, 2015
    Date of Patent: May 23, 2017
    Assignee: Climax Technology Co., Ltd.
    Inventors: Cheng-Wei Chen, Meng-Chih Lin, Dau-Chyrh Chang
  • Inhibitors of Bruton's tyrosine kinase
    Patent number: 9656988
    Abstract: Disclosed herein are reversible and irreversible inhibitors of Bruton's tyrosine kinase (Btk). Also disclosed are pharmaceutical compositions that include the compounds. Methods of using the Btk inhibitors are described, alone or in combination with other therapeutic agents, for the treatment of autoimmune diseases or conditions, heteroimmune diseases or conditions, cancer, including lymphoma, and inflammatory diseases or conditions.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: May 23, 2017
    Assignee: PHARMACYCLICS LLC
    Inventors: Wei Chen, Zhaozhong J. Jia, William D. Thomas
  • Wafer level shielding in multi-stacked fan out packages and methods of forming same
    Patent number: 9659878
    Abstract: An embodiment device package includes a device die, a molding compound surrounding the device die, a conductive through inter-via (TIV) extending through the molding compound, and an electromagnetic interference (EMI) shield disposed over and extending along sidewalls of the molding compound. The EMI shield contacts the conductive TIV, and the conductive TIV electrically connects the EMI shield to an external connector. The external connector and the EMI shield are disposed on opposing sides of the device die.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yu Chen, Hsien-Wei Chen, An-Jhih Su, Jo-Mei Wang, Tien-Chung Yang
  • Display
    Patent number: 9659530
    Abstract: A display is disclosed. The display comprises a panel, a data driver and a scan driver. The panel comprises pixels, data lines and scan lines. The data lines transmit data signals to the pixels, and the scan lines transmit scan signals to the pixels. The data driver provides the data signals, and the scan driver provides the scan signals. The scan driver comprises a shift register circuit. The shift register circuit comprises an i+1th stage carry shift register, an ith stage carry shift register and a jth stage buffer shift register. The ith stage carry shift register generates an i+1th start signal to start the i+1th stage carry shift register, so that the i+1th stage carry shift register generates an i+2th start signal. The i+1th start signal starts the jth stage buffer shift register to generate a jth output signal.
    Type: Grant
    Filed: July 29, 2015
    Date of Patent: May 23, 2017
    Assignee: INNOLUX CORPORATION
    Inventors: Li-Wei Sung, Yen-Wei Chen, Chung-Lin Tsai
  • Semiconductor devices, multi-die packages, and methods of manufacture thereof
    Patent number: 9659863
    Abstract: Semiconductor device, multi-die packages, and methods of manufacture thereof are described. In an embodiment, a semiconductor device may include: first conductive pillars and second conductive pillars respectively aligned to a first row of first pins and a second row of second pins of a first die, the first pins and the second pins differing in function; a first insulating layer covering surfaces of the first conductive pillars and the second conductive pillars facing away from the first die; first pads disposed on a surface of the first insulating layer facing away from the first die, the first pads substantially aligned to the first conductive pillars; and first traces coupled to the first pads, the first traces extending over a portion of the first insulating layer covering the second conductive pillars.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: May 23, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Hsien-Wei Chen, An-Jhih Su, Chi-Hsi Wu, Der-Chyang Yeh, Shih-Peng Tai
  • Liquid crystal display device and driving method thereof
    Patent number: 9659537
    Abstract: The disclosure is related to a liquid crystal display device, including a liquid crystal display panel and a gamma generator including a first storage unit storing a group of positive or negative gamma voltage values and a second storage unit storing a group of negative or positive gamma voltage values. The gamma generator periodically obtains the group of the positive or negative gamma voltage values, or the group of the positive or negative gamma voltage values according to a control of a polarity inversion signal. The liquid crystal display panel displays an image according to the group of the positive and/or the group of the negative gamma voltage values. The difference between the disclosure and the current technique is that the cost is decreased effectively; meanwhile, the driving structure is simplified, a wiring area is decreased and it is favorable for a narrow frame design.
    Type: Grant
    Filed: January 16, 2015
    Date of Patent: May 23, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd.
    Inventors: Jiehui Qin, Xiaoping Tan, Wei Chen
  • ZEA MAYS REGULATORY ELEMENTS AND USES THEREOF
    Publication number: 20170137834
    Abstract: Provided are constructs and methods for expressing a transgene in plant cells and/or plant tissues using Zea mays GRMZM2G015295 gene regulatory elements.
    Type: Application
    Filed: October 21, 2016
    Publication date: May 18, 2017
    Applicant: Dow AgroSciences LLC
    Inventors: Manju Gupta, Sandeep Kumar, Navin Elango, Jeffrey Beringer, Shavell Gorman, Andrew F. Worden, Sara Bennett, Daren Hemingway, Wei Chen, Huixia Wu, Ning Zhou, Michelle Sprint Smith
  • RRAM CELL STRUCTURE WITH LATERALLY OFFSET BEVA/TEVA
    Publication number: 20170141301
    Abstract: The present disclosure relates to a resistive random access memory (RRAM) device. The RRAM device has a bottom electrode arranged over a bottom electrode via. A variable resistive dielectric layer is arranged over the bottom electrode. The variable resistive dielectric layer extends to within a recess in an upper surface of the bottom electrode. A top electrode is disposed over the variable resistive dielectric layer. A top electrode via extends outward from an upper surface of the top electrode at a position centered along a first axis that is laterally offset from a second axis centered upon the recess within the upper surface of the bottom electrode.
    Type: Application
    Filed: July 29, 2016
    Publication date: May 18, 2017
    Inventors: Chih-Yang Chang, Wen-Ting Chu, Kuo-Chi Tu, Yu-Wen Liao, Hsia-Wei Chen, Chin-Chieh Yang, Sheng-Hung Shih, Wen-Chun You
  • APPARATUS FOR UV FLOWABLE DIELECTRIC
    Publication number: 20170137943
    Abstract: Provided are methods and apparatus for ultraviolet (UV) assisted capillary condensation to form dielectric materials. In some embodiments, a UV driven reaction facilitates photo-polymerization of a liquid phase flowable material. Applications include high quality gap fill in high aspect ratio structures and por sealing of a porous solid dielectric film. According to various embodiments, single station and multi-station chambers configured for capillary condensation and UV exposure are provided.
    Type: Application
    Filed: November 16, 2015
    Publication date: May 18, 2017
    Inventors: Jonathan D. Mohn, Nicholas Muga Ndiege, Patrick A. Van Cleemput, David Fang Wei Chen, Wenbo Liang, Shawn M. Hamilton
  • Package with Solder Regions Aligned to Recesses
    Publication number: 20170141054
    Abstract: A method includes forming a passivation layer over a portion of a metal pad, forming a polymer layer over the passivation layer, and exposing the polymer layer using a photolithography mask. The photolithography mask has an opaque portion, a transparent portion, and a partial transparent portion. The exposed polymer layer is developed to form an opening, wherein the metal pad is exposed through the opening. A Post-Passivation Interconnect (PPI) is formed over the polymer layer, wherein the PPI includes a portion extending into the opening to connect to the metal pad.
    Type: Application
    Filed: January 27, 2017
    Publication date: May 18, 2017
    Inventors: Ching-Jung Yang, Hsien-Wei Chen, Hsien-Ming Tu, Chang-Pin Huang, Yu-Chia Lai, Tung-Liang Shao