Patents by Inventor Wei-Ti Liu
Wei-Ti Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11895191Abstract: A mobile Internet-of-Things (IoT) edge device, comprising a reconfigurable processor unit including a substrate; a die stack coupled to the substrate and having a field-programmable gate array (FPGA) die element and a reconfigurable die element capable of serving as storage memory or as configuration memory based on configuration information; and a processor coupled to the substrate and configured to cooperate with the die stack for processing data; and a processor-independent connectivity unit coupled to the reconfigurable processor unit and including an antenna; a radio-frequency chip (RFIC) coupled to the antenna and configured to receive incoming signals and transmit outgoing signals over the antenna; circuitry configured to translate the incoming signals to incoming data or transmit the outgoing data to outgoing signals; and a system interface configured to transmit the incoming data to the reconfigurable processor unit for processing, and configured to receive the outgoing data from the reconfigurable pType: GrantFiled: August 9, 2022Date of Patent: February 6, 2024Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Sr., Wei-Ti Liu, Darrel James Guzy, Jr.
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Patent number: 11797067Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: GrantFiled: August 1, 2022Date of Patent: October 24, 2023Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Patent number: 11762440Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: GrantFiled: August 1, 2022Date of Patent: September 19, 2023Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Publication number: 20230100530Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: ApplicationFiled: August 1, 2022Publication date: March 30, 2023Inventors: Darrel James Guzy, Wei-Ti Liu
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Publication number: 20220382697Abstract: A mobile Internet-of-Things (IoT) edge device, comprising a reconfigurable processor unit including a substrate; a die stack coupled to the substrate and having a field-programmable gate array (FPGA) die element and a reconfigurable die element capable of serving as storage memory or as configuration memory based on configuration information; and a processor coupled to the substrate and configured to cooperate with the die stack for processing data; and a processor-independent connectivity unit coupled to the reconfigurable processor unit and including an antenna; a radio-frequency chip (RFIC) coupled to the antenna and configured to receive incoming signals and transmit outgoing signals over the antenna; circuitry configured to translate the incoming signals to incoming data or transmit the outgoing data to outgoing signals; and a system interface configured to transmit the incoming data to the reconfigurable processor unit for processing, and configured to receive the outgoing data from the reconfigurable pType: ApplicationFiled: August 9, 2022Publication date: December 1, 2022Inventors: Darrel James Guzy, SR., Wei-Ti Liu, Darrel James Guzy, JR.
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Patent number: 11463524Abstract: A mobile Internet-of-Things (IoT) edge device, comprising a reconfigurable processor unit including a substrate; a die stack coupled to the substrate and having a field-programmable gate array (FPGA) die element and a reconfigurable die element capable of serving as storage memory or as configuration memory based on configuration information; and a processor coupled to the substrate and configured to cooperate with the die stack for processing data; and a processor-independent connectivity unit coupled to the reconfigurable processor unit and including an antenna; a radio-frequency chip (RFIC) coupled to the antenna and configured to receive incoming signals and transmit outgoing signals over the antenna; circuitry configured to translate the incoming signals to incoming data or transmit the outgoing data to outgoing signals; and a system interface configured to transmit the incoming data to the reconfigurable processor unit for processing, and configured to receive the outgoing data from the reconfigurable pType: GrantFiled: June 15, 2021Date of Patent: October 4, 2022Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Sr., Wei-Ti Liu, Darrel James Guzy, Jr.
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Patent number: 11435800Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: GrantFiled: July 13, 2021Date of Patent: September 6, 2022Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Patent number: 11402886Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: GrantFiled: July 13, 2021Date of Patent: August 2, 2022Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Publication number: 20220121257Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: ApplicationFiled: July 13, 2021Publication date: April 21, 2022Applicant: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Publication number: 20210409494Abstract: A mobile Internet-of-Things (IoT) edge device, comprising a reconfigurable processor unit including a substrate; a die stack coupled to the substrate and having a field-programmable gate array (FPGA) die element and a reconfigurable die element capable of serving as storage memory or as configuration memory based on configuration information; and a processor coupled to the substrate and configured to cooperate with the die stack for processing data; and a processor-independent connectivity unit coupled to the reconfigurable processor unit and including an antenna; a radio-frequency chip (RFIC) coupled to the antenna and configured to receive incoming signals and transmit outgoing signals over the antenna; circuitry configured to translate the incoming signals to incoming data or transmit the outgoing data to outgoing signals; and a system interface configured to transmit the incoming data to the reconfigurable processor unit for processing, and configured to receive the outgoing data from the reconfigurable pType: ApplicationFiled: June 15, 2021Publication date: December 30, 2021Applicant: Arbor Company, LLLPInventors: Darrel James Guzy, SR., Wei-Ti Liu, Darrel James Guzy, JR.
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Patent number: 11061455Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: GrantFiled: September 22, 2020Date of Patent: July 13, 2021Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Patent number: 10969977Abstract: An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array blocks, each reconfigurable memory array block being capable of configuration and reconfiguration as a storage memory array block or as a control logic array block for controlling at least a portion of the one or more FPGA elements; and a control logic circuit functioning to configure each reconfigurable memory array block as the respective memory array block or as the respective logic array block for controlling the one or more FPGA elements.Type: GrantFiled: September 25, 2020Date of Patent: April 6, 2021Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Publication number: 20210011641Abstract: An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array blocks, each reconfigurable memory array block being capable of configuration and reconfiguration as a storage memory array block or as a control logic array block for controlling at least a portion of the one or more FPGA elements; and a control logic circuit functioning to configure each reconfigurable memory array block as the respective memory array block or as the respective logic array block for controlling the one or more FPGA elements.Type: ApplicationFiled: September 25, 2020Publication date: January 14, 2021Applicant: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Publication number: 20210004070Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: ApplicationFiled: September 22, 2020Publication date: January 7, 2021Applicant: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Publication number: 20200341662Abstract: An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array blocks, each reconfigurable memory array block being capable of configuration and reconfiguration as a storage memory array block or as a control logic array block for controlling at least a portion of the one or more FPGA elements; and a control logic circuit functioning to configure each reconfigurable memory array block as the respective memory array block or as the respective logic array block for controlling the one or more FPGA elements.Type: ApplicationFiled: March 5, 2020Publication date: October 29, 2020Applicant: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Patent number: 10802735Abstract: An integrated circuit die element comprises one or more field-programmable gate arrays (FPGAs) elements; a reconfigurable dual function memory array, the reconfigurable dual function memory array including a plurality of reconfigurable memory array blocks, each reconfigurable memory array block being capable of configuration and reconfiguration as a storage memory array block or as a control logic array block for controlling at least a portion of the one or more FPGA elements; and a control logic circuit functioning to configure each reconfigurable memory array block as the respective memory array block or as the respective logic array block for controlling the one or more FPGA elements.Type: GrantFiled: March 5, 2020Date of Patent: October 13, 2020Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Patent number: 10782759Abstract: A system comprises an integrated circuit die substrate; volatile memory electrically coupled to the integrated circuit die substrate; a first integrated circuit die element electrically coupled to the integrated circuit die substrate, the first integrated circuit die element comprising a first field programmable gate array (FPGA), and the first integrated circuit die element disposed adjacent to the volatile memory; a battery charger operable to receive power from a main power supply, the main power supply having an on state and an off state, wherein the main power supply is supplying power in the on state and not supplying power in the off state; and a battery module disposed on a top portion of the first integrated circuit die element, the battery module operable to receive power from the battery charger, and the battery module operable to supply power to the volatile memory at least when the main power supply is in the off state.Type: GrantFiled: March 5, 2020Date of Patent: September 22, 2020Assignee: Arbor Company, LLLPInventors: Darrel James Guzy, Wei-Ti Liu
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Publication number: 20120237024Abstract: One embodiment of the invention is based on the recognition that by keeping the encryption key (DEK) in a key device, and using the key device to perform all encryption and decryption, where the DEK is not supplied to the computing system, the above noted security problems can be overcome. The encrypted information is stored in the computing system and not in the key device. However, without the key device, it is not possible to access the encrypted information stored in the computing system. Thus, the function of the key device is similar to that of a physical key used in daily life for unlocking a door or drawer, except that the user gains access to protected information instead of access to a building, drawer or car.Type: ApplicationFiled: March 18, 2011Publication date: September 20, 2012Inventors: Wei-Ti Liu, Adam Chen, Kevin Wayne Do, Reid Augustin
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Patent number: 4833349Abstract: An output driver circuit is described which can be programmed by the user into tri-state or open-collector configurations, depending on the needs of the user. The driver circuit comprises a pair of a first pull-up and a pull-down FET transistor. The source of the pull-up transistor and drain of the pull-down transistor are both connected to the output of the driver. The gates of the pair of transistors are controlled by an input signal and its complement. The driver further includes a second pull-up FET whose source is connected to the output of the driver. The channel width to channel length ratio of the second pull-up transistor is at least about an order of magnitude greater than that of the first pull-up transistor. The driver further includes a control means responsive to the input signal for applying a second signal to the gate of the second pull-up transistor for programming the driver into tri-state or open-collector modes.Type: GrantFiled: September 1, 1987Date of Patent: May 23, 1989Assignee: PLX TechnologyInventors: Wei-Ti Liu, D. James Guzy, Jr., Michael J. Salameh
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Patent number: 4689495Abstract: A CMOS high voltage switch for interfaceing between a decoder output and an input to an erasable, programmable read-only-memory includes an inverter for receiving an input signal from the output of the decoder. A N-channel MOS pass transistor has a conduction path and a gate electrode. One end of the conduction path is connected to the output of the inverter, and the other end of the conduction path is connected to an output node. The gate electrode of the pass transistor is connected to a first lower supply potential. A pumping device is connected to the other end of the conduction path for pumping the output node to a first higher voltage during a first mode of operation. A P-channel MOS switching transistor is also connected to the other end of the conduction path for switching the output node to a second lower voltage during a second mode of operation.Type: GrantFiled: June 17, 1985Date of Patent: August 25, 1987Assignee: Advanced Micro Devices, Inc.Inventor: Wei-Ti Liu