Abstract: A bias generator circuit includes a first high voltage for biasing a N-well region and a second delayed and lower voltage biasing a source region of a P-channel field-effect transistor so as to increase latch-up immunity. The generator circuit includes a high voltage generator and a multiplier circuit responsive to a power supply voltage for generating a first voltage level for biasing the N-well region. A delay network is responsive to the first voltage for generating a delay voltage. A level detection circuit is responsive to the delay voltage and the power supply voltage for generating a control signal when the delayed voltage reaches a predetermined level. A control device is responsive to the control signal for generating a second voltage for biasing the source region of the P-channel field-effect transistor. The second voltage level is delayed and lower than the first voltage level so that the PN junction is reverse biased to increase latch-up immunity.

Abstract: An MOS buffer is described which converts TTL level signals to MOS level signals. An inverter which receives the input TTL signal is coupled to ground through a reference voltage source. This source assures that the inverter does not conduct when the TTL level signal is in its lower state. The output of the inverter is coupled to a level shifter which assures that the output of the inverter is shifted downward when the TTL signal is in its higher state. The transistors in the buffer may have short channels unlike prior art circuits.