Patents by Inventor Wei Ting Chien

Wei Ting Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210098599
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Application
    Filed: December 14, 2020
    Publication date: April 1, 2021
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Publication number: 20200411672
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Application
    Filed: September 6, 2020
    Publication date: December 31, 2020
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Patent number: 10868142
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Grant
    Filed: January 11, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Patent number: 10770570
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: September 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Publication number: 20200259001
    Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant decreasing in a direction extending from a top of the fin to a bottom of the fin.
    Type: Application
    Filed: April 29, 2020
    Publication date: August 13, 2020
    Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
  • Patent number: 10665697
    Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant increasing in a direction extending from a top of the fin to a bottom of the fin.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
  • Publication number: 20200135889
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a sacrificial gate structure over an active region. A first spacer layer is formed along sidewalls and a top surface of the sacrificial gate structure. A first protection layer is formed over the first spacer layer. A second spacer layer is formed over the first protection layer. A third spacer layer is formed over the second spacer layer. The sacrificial gate structure is replaced with a replacement gate structure. The second spacer layer is removed to form an air gap between the first protection layer and the third spacer layer.
    Type: Application
    Filed: January 11, 2019
    Publication date: April 30, 2020
    Inventors: Wei-Ting Chien, Liang-Yin Chen, Yi-Hsiu Liu, Tsung-Lin Lee, Huicheng Chang
  • Patent number: 10529861
    Abstract: FinFET structures and methods of forming the same are disclosed. A device includes a semiconductor fin. A gate stack is on the semiconductor fin. The gate stack includes a gate dielectric on the semiconductor fin and a gate electrode on the gate dielectric. The gate electrode and the gate dielectric have top surfaces level with one another. A first inter-layer dielectric (ILD) is adjacent the gate stack over the semiconductor fin. The first ILD exerts a compressive strain on the gate stack.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Wei-Ting Chien, Chun-Feng Nieh, Wen-Li Chiu, Huicheng Chang, Chun-Sheng Liang
  • Publication number: 20190386118
    Abstract: In an embodiment, a device includes: a fin on a substrate, fin having a Si portion proximate the substrate and a SiGe portion distal the substrate; a gate stack over a channel region of the fin; a source/drain region adjacent the gate stack; a first doped region in the SiGe portion of the fin, the first doped region disposed between the channel region and the source/drain region, the first doped region having a uniform concentration of a dopant; and a second doped region in the SiGe portion of the fin, the second doped region disposed under the source/drain region, the second doped region having a graded concentration of the dopant increasing in a direction extending from a top of the fin to a bottom of the fin.
    Type: Application
    Filed: June 15, 2018
    Publication date: December 19, 2019
    Inventors: Chia-Ling Chan, Liang-Yin Chen, Wei-Ting Chien
  • Patent number: 10473279
    Abstract: A wide-angle linear LED lighting device includes a polygonal lampshade, a base and at least two LED modules. The polygonal lampshade includes at least two lateral parts and an installation part. The base is disposed within the polygonal lampshade and disposed on an inner surface of the installation part. There is an included angle between the base and the inner surface of the installation part. The at least two LED modules are disposed on the base. The light beams emitted by the at least two LED modules are outputted from different lateral parts of the polygonal lampshade. The light-outputting characteristics of the wide-angle linear LED lighting device are correlated with the included angle and the at least two LED modules.
    Type: Grant
    Filed: January 25, 2017
    Date of Patent: November 12, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Ting Chien, Chia-Wen Hsu
  • Publication number: 20190067458
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 28, 2019
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li, Tien-Shun Chang
  • Patent number: 10115808
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: October 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Tien-Shun Chang, Wei-Ting Chien, Chih-Pin Tsao, Hou-Ju Li
  • Patent number: 10041994
    Abstract: A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.
    Type: Grant
    Filed: November 10, 2016
    Date of Patent: August 7, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Wei-Ting Chien, Yueqin Zhu, Yongliang Song, Yong Zhao
  • Publication number: 20180209598
    Abstract: A wide-angle linear LED lighting device includes a polygonal lampshade, a base and at least two LED modules. The polygonal lampshade includes at least two lateral parts and an installation part. The base is disposed within the polygonal lampshade and disposed on an inner surface of the installation part. There is an included angle between the base and the inner surface of the installation part. The at least two LED modules are disposed on the base. The light beams emitted by the at least two LED modules are outputted from different lateral parts of the polygonal lampshade. The light-outputting characteristics of the wide-angle linear LED lighting device are correlated with the included angle and the at least two LED modules.
    Type: Application
    Filed: January 25, 2017
    Publication date: July 26, 2018
    Inventors: Wei-Ting Chien, Chia-Wen Hsu
  • Patent number: 10032580
    Abstract: A device for inputting commands includes a casing, a rotatable disk, and a processor. The rotatable disk can rotate relative to the casing, and has a plurality of input modes. The rotatable disk includes a switch button for switching among the input modes. The rotatable disk further includes a pointer. The casing includes an annular area surrounding the rotatable disk. The annular area has a plurality of input positions. The input positions correspond to characters of one character set corresponding to the current input mode. The processor is received in the casing, and can generate a command or control signal according to a character corresponding to an input position when the pointer is aligned with the input position.
    Type: Grant
    Filed: June 6, 2017
    Date of Patent: July 24, 2018
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chun-Hung Lai, Chih-Chun Chang, Ming-Yi Liu, Wei-Ting Chien
  • Publication number: 20180151706
    Abstract: A finFET device and methods of forming a finFET device are provided. The method includes depositing a dummy gate over and along sidewalls of a fin extending upwards from a semiconductor substrate, forming a first gate spacer along a sidewall of the dummy gate, and plasma-doping the first gate spacer with carbon to form a carbon-doped gate spacer. The method further includes forming a source/drain region adjacent a channel region of the fin and diffusing carbon from the carbon-doped gate spacer into a first region of the fin to provide a first carbon-doped region. The first carbon-doped region is disposed between at least a portion of the source/drain region and the channel region of the fin.
    Type: Application
    Filed: June 1, 2017
    Publication date: May 31, 2018
    Inventors: Yu-Chang Lin, Chun-Feng Nieh, Huicheng Chang, Tien-Shun Chang, Wei-Ting Chien, Chin-Pin Tsao, Hou-Ju Li
  • Publication number: 20180145177
    Abstract: FinFET structures and methods of forming the same are disclosed. A device includes a semiconductor fin. A gate stack is on the semiconductor fin. The gate stack includes a gate dielectric on the semiconductor fin and a gate electrode on the gate dielectric. The gate electrode and the gate dielectric have top surfaces level with one another. A first inter-layer dielectric (ILD) is adjacent the gate stack over the semiconductor fin. The first ILD exerts a compressive strain on the gate stack.
    Type: Application
    Filed: November 18, 2016
    Publication date: May 24, 2018
    Inventors: Yu-Chang Lin, Wei-Ting Chien, Chun-Feng Nieh, Wen-Li Chiu, Huicheng Chang, Chun-Sheng Liang
  • Publication number: 20170285099
    Abstract: A method for predicting high-temperature operating life of an integrated circuit (IC) includes performing bias temperature instability tests and high-temperature operating life tests on a device of the IC, establishing a relationship between the device bias temperature instability and the IC's high-temperature operating life based on a result of the bias temperature instability tests and the high-temperature operating life tests. The method further includes providing a lot of subsequent integrated circuits (ICs), performing wafer-level bias temperature instability tests on a device of the ICs, and predicting high-temperature operating life of the ICs based on a result of the wafer-level bias temperature instability tests and based on the established relationship between the device's bias temperature instability and the IC's high-temperature operating life. The method can save significant effort and time over conventional approaches for accurate prediction of high-temperature operating life of an IC.
    Type: Application
    Filed: November 10, 2016
    Publication date: October 5, 2017
    Inventors: Wei-Ting CHIEN, Yueqin ZHU, Yongliang SONG, Yong ZHAO
  • Patent number: D867650
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 19, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chung-Chieh Cheng, Kun-Ming Tien, Ying-Hao Huang, Wei-Ting Chien, Yen-Jyh Lai
  • Patent number: D869738
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 10, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chung-Chieh Cheng, Kun-Ming Tien, Ying-Hao Huang, Wei-Ting Chien, Yen-Jyh Lai