Patents by Inventor Wei-Ting Huang

Wei-Ting Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200058534
    Abstract: Apparatus and methods for handling die carriers are disclosed. In one example, a disclosed apparatus includes: a load port configured to load a die carrier operable to hold a plurality of dies into a processing tool; and a lane changer coupled to the load port and configured to move at least one die in the die carrier to an input of the processing tool and transfer the at least one die into the processing tool for processing the at least one die.
    Type: Application
    Filed: July 30, 2019
    Publication date: February 20, 2020
    Inventors: Tsung-Sheng KUO, Kai-Chieh HUANG, Wei-ting HSIAO, Yang-Ann CHU, 1-Lun YANG, Hsuan LEE
  • Publication number: 20200052159
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Application
    Filed: October 21, 2019
    Publication date: February 13, 2020
    Applicant: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Patent number: 10529916
    Abstract: An integrated circuit device includes a substrate and a magnetic tunneling junction (MTJ). The MTJ includes at least a pinned layer, a barrier layer, and a free layer. The MTJ is formed over a surface of the substrate. Of the pinned layer, the barrier layer, and the free layer, the free layer is formed first and is closest to the surface. This enables a spacer to be formed over a perimeter region of the free layer prior to etching the free layer. Any damage to the free layer that results from etching or other free layer edge-defining process is kept at a distance from the tunneling junction by the spacer.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Hang Huang, Fu-Ting Sung, Chern-Yow Hsu, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 10510664
    Abstract: A semiconductor device and methods of formation are provided. A semiconductor device includes an annealed cobalt plug over a silicide in a first opening of the semiconductor device, wherein the annealed cobalt plug has a repaired lattice structure. The annealed cobalt plug is formed by annealing a cobalt plug at a first temperature for a first duration, while exposing the cobalt plug to a first gas. The repaired lattice structure of the annealed cobalt plug is more regular or homogenized as compared to a cobalt plug that is not so annealed, such that the annealed cobalt plug has a relatively increased conductivity or reduced resistivity.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hong-Mao Lee, Huicheng Chang, Chia-Han Lai, Chi-Hsuan Ni, Cheng-Tung Lin, Huang-Yi Huang, Chi-Yuan Chen, Li-Ting Wang, Teng-Chun Tsai, Wei-Jung Lin
  • Patent number: 10510406
    Abstract: An operating method of the soft-verify write assist circuit of the resistive memory provides a voltage level applying step, a write operating step and a write voltage controlling step. The voltage level applying step is for applying a plurality of voltage levels to the reference voltage, the word line and the switching signal, respectively. The write operating step is for driving the memory cell to perform in a set process or a reset process via the first three-terminal switching element, the second three-terminal switching element and the soft-verify controlling unit during a write operation. The write voltage controlling step is for controlling the write voltage to be increased in the ramping cycle and decreased in the soft-verify cycle.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: December 17, 2019
    Assignee: NATIONAL TSING HUA UNIVERSITY
    Inventors: Meng-Fan Chang, Huan-Ting Lin, Tsung-Yuan Huang, Wei-Hao Chen, Han-Wen Hu
  • Patent number: 10504422
    Abstract: A display panel and a compensation circuit are provided. The display panel has a periphery region and a display region. The display panel includes pixel columns and a threshold voltage compensation circuit. The pixel columns are disposed in the display region. The threshold voltage compensation circuit is disposed in the periphery region. The threshold voltage compensation circuit receives a compensation voltage, outputs threshold voltage information of a compensation transistor based on the compensation voltage, and generates compensated display data based on the threshold voltage information and display data.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: December 10, 2019
    Assignee: Au Optronics Corporation
    Inventors: Mao-Hsun Cheng, Cheng-Han Huang, Wei-Ting Wu, Yung-Chih Chen
  • Publication number: 20190359776
    Abstract: An amphiphilic polymer, an amphiphilic polymer manufacturing method, a contact lens material including the amphiphilic polymer, and contact lens manufacturing method are provided. The amphiphilic polymer includes poly(dimethylsiloxane) and amphiphilic chitosan bonded to the same. The contact lens material includes the amphiphilic polymer. The amphiphilic polymer manufacturing method includes providing a poly(dimethylsiloxane), providing an amphiphilic chitosan, and bonding the amphiphilic chitosan to the poly(dimethylsiloxane).
    Type: Application
    Filed: January 30, 2019
    Publication date: November 28, 2019
    Applicant: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Yun-Ru HSIEH, Dean-Mo LIU, Yu-Cheng JIAN, Wei-Ting HUANG
  • Patent number: 10491760
    Abstract: An image transmission device includes a CPU, and a wireless communication module, a button, a USB connector and an internal storage unit connected with the CPU. The USB connector is inserted into a computer having a portable software. The internal storage unit is inaccessible to the computer. The portable software is copied or downloaded to the computer from an external source and executed by the computer. The wireless communication module is wirelessly connected with a receiving device. When the button is activated, a signal is transmitted to the CPU and a command is transmitted to the portable software by the CPU to execute screen mirroring control, so that images are transmitted from the computer to the receiving device through the USB connector and the wireless communication module. The safety and application diversity are effectively enhanced, and the one-button screen mirroring is realized.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 26, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Botao Lin, Cho-Cheng Lin, Ya-Ting Huang, Wei-Chi Shih
  • Publication number: 20190333926
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a first gate electrode formed over the substrate. The semiconductor structure further includes a dielectric layer formed on a sidewall of the first gate electrode and a second gate electrode formed over the substrate and separated from the first gate electrode by the dielectric layer. The semiconductor structure further includes a contact formed over the second gate electrode. In addition, the contact has a first extending portion and a second extending portion extending along opposite sidewalls of the second gate electrode.
    Type: Application
    Filed: July 12, 2019
    Publication date: October 31, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting SUNG, Chung-Chiang MIN, Wei-Hang HUANG, Shih-Chang LIU, Chia-Shiung TSAI
  • Patent number: 10453999
    Abstract: The invention provides an LED including a first-type semiconductor layer, an emitting layer, a second-type semiconductor layer, a first electrode, a second electrode, a Bragg reflector structure, a conductive layer and insulation patterns. The first electrode and the second electrode are located on the same side of the Bragg reflector structure. The conductive layer is disposed between the Bragg reflector structure and the second-type semiconductor layer. The insulation patterns are disposed between the conductive layer and the second-type semiconductor layer. Each insulating layer has a first surface facing toward the second-type semiconductor layer, a second surface facing away from the second-type semiconductor layer, and an inclined surface. The inclined surface connects the first surface and the second surface and is inclined with respect to the first surface and the second surface.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: October 22, 2019
    Assignee: Genesis Photonics Inc.
    Inventors: Yi-Ru Huang, Tung-Lin Chuang, Yan-Ting Lan, Sheng-Tsung Hsu, Chih-Ming Shen, Jing-En Huang, Teng-Hsien Lai, Hung-Chuan Mai, Kuan-Chieh Huang, Shao-Ying Ting, Cheng-Pin Chen, Wei-Chen Chien, Chih-Chin Cheng, Chih-Hung Tseng
  • Publication number: 20190314942
    Abstract: A universal jig is provided for clamping wind turbine blades. The jig has a rectangle-like shape forming a space for clamping a blade at the blade root or the blade body. The jig comprises a set of vertically-moving parts; a set of horizontally-moving parts; a plurality of adjusted pads; and a plurality of positioning parts. The vertically-moving parts comprise two upper connecting posts and two lower connecting posts sheathed with each other separately to form two length sides of the jig. The horizontally-moving parts comprise two left connecting posts and two right connecting posts. The adjusted pads are locked on the left and the right connecting posts. The positioning parts are locked at the upper and the lower connecting posts of the length sides of the jig and are locked at the left and the right connecting posts of the width sides of the jig.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 17, 2019
    Inventors: Yu-Chu Lin, Yan-Ting Lin, Wei-Nian Su, Chin-Cheng Huang
  • Publication number: 20190303286
    Abstract: An apparatus and a method for accessing a plurality of memory blocks is disclosed. The An apparatus comprises: a memory circuit configured to store a recording table, wherein the recording table corresponds to quality index of the plurality of memory blocks; and a control circuit configured to group the plurality of memory blocks to a first memory group and a second memory group according to the quality index; to enable to access the memory blocks in the first memory group, and to disable to access the memory blocks in the second memory group.
    Type: Application
    Filed: March 27, 2019
    Publication date: October 3, 2019
    Inventors: Yen-Chung Chen, Chih-Ching Chien, Li-Chun Huang, Han-Ting Tsai, Wei-Ren Hsu
  • Patent number: 10424622
    Abstract: A display device comprised of OLEDs and micro LEDs which allows for blue light degradation of the OLEDs includes a first substrate and a second substrate in a double-decked configuration. First light emitting elements are located and spaced on the first substrate and second light emitting elements are located and spaced on the second substrate, the light emitting elements on the lower deck being staggered so as not to be hidden by the light emitting elements on the upper deck. The upper deck has openings (or is transparent) therein to allow egress of light from the light emitting elements of the lower deck. The display device provides a solution for uneven display cause by degradation of pixels.
    Type: Grant
    Filed: July 4, 2018
    Date of Patent: September 24, 2019
    Assignee: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Chang-Ting Lin, Wei-Chih Chang, Ying-Chieh Chen, Chung-Wen Lai, Chun-Chieh Huang, Wei-Li Wang, Po-Yi Lu, Jen-Jie Chen, I-Wei Wu
  • Publication number: 20190243057
    Abstract: The present subject matter describes illuminating a display panel. In an example implementation, a plurality of light guide films is stacked together, with a light guide film positioned over another light guide film of the plurality of light guide films. Each of the light guide films of the plurality is associated with a light source. The light source for a respective light guide film is to launch light through at least one light incident surface of the respective light guide film, where the light guide assembly is to guide light from the light source to illuminate the display panel.
    Type: Application
    Filed: October 26, 2016
    Publication date: August 8, 2019
    Inventors: WEI-KUANG CHU, KUAN-TING WU, KOU-CHIH HUANG
  • Publication number: 20190237006
    Abstract: A display panel and a compensation circuit are provided. The display panel has a periphery region and a display region. The display panel includes pixel columns and a threshold voltage compensation circuit. The pixel columns are disposed in the display region. The threshold voltage compensation circuit is disposed in the periphery region. The threshold voltage compensation circuit receives a compensation voltage, outputs threshold voltage information of a compensation transistor based on the compensation voltage, and generates compensated display data based on the threshold voltage information and display data.
    Type: Application
    Filed: December 18, 2018
    Publication date: August 1, 2019
    Applicant: Au Optronics Corporation
    Inventors: Mao-Hsun Cheng, Cheng-Han Huang, Wei-Ting Wu, Yung-Chih Chen
  • Patent number: 10355011
    Abstract: Methods for forming semiconductor structures are provided. The method for forming the semiconductor structure includes forming a control gate over a substrate and forming a dielectric layer covering the control gate. The method further includes forming a conductive layer having a first portion and a second portion over the dielectric layer. In addition, the first portion of the conductive layer is separated from the control gate by the dielectric layer. The method further includes forming an oxide layer on a top surface of the first portion of the conductive layer and removing the second portion of the conductive layer to form a memory gate.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: July 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Fu-Ting Sung, Chung-Chiang Min, Wei-Hang Huang, Shih-Chang Liu, Chia-Shiung Tsai
  • Publication number: 20190213933
    Abstract: A head mounted display includes a body portion, a display panel, a lens module, an infrared transmitter, and an infrared receiver. The display panel is provided in the body portion. The lens module is disposed in front of the display panel, and includes an outer frame, a lens and a mounting portion. The lens is provided in the outer frame. The mounting portion is disposed at the periphery of the outer frame. A reference line is connected between the viewing point and the mounting portion. The infrared transmitter is disposed on the mounting portion. The outer frame is provided with a light exit surface between the viewing point and the mounting portion. The infrared transmitter projects a light along the reference line via the light exit surface which limits the exit angle of the light. The infrared receiver is disposed on the body portion for receiving the light.
    Type: Application
    Filed: March 5, 2018
    Publication date: July 11, 2019
    Applicant: Acer Incorporated
    Inventors: Shih-Ting Huang, Wei-Kuo Shih
  • Publication number: 20190181135
    Abstract: A control circuit providing an output voltage and including an N-type transistor, a first P-type transistor and a second P-type transistor is provided. The N-type transistor is coupled to a first power terminal. The first P-type transistor includes a first source, a first drain, a first gate and a first bulk. The first gate is coupled to a gate of the N-type transistor. The first bulk is coupled to the first source. The second P-type transistor includes a second source, a second drain, a second gate and a second bulk. The second source is coupled to a second power terminal. The second drain and the second bulk are coupled to the first bulk.
    Type: Application
    Filed: December 12, 2017
    Publication date: June 13, 2019
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Shao-Chang HUANG, Shang-Chuan PAI, Wei-Chung WU, Szu-Chi CHEN, Sheng-Chih CHUANG, Yin-Ting LIN, Pei-Chun YU, Han-Pei LIU, Jung-Tsun CHUANG, Chieh-Yao CHUANG, Hung-Wei CHEN
  • Patent number: D867650
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: November 19, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chung-Chieh Cheng, Kun-Ming Tien, Ying-Hao Huang, Wei-Ting Chien, Yen-Jyh Lai
  • Patent number: D869738
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: December 10, 2019
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Chung-Chieh Cheng, Kun-Ming Tien, Ying-Hao Huang, Wei-Ting Chien, Yen-Jyh Lai