Abstract: A semiconductor device includes an insulating layer embedding a gate electrode and overlying a substrate, a stack of a gate dielectric including a gate dielectric material, a dielectric diffusion barrier liner including a dielectric diffusion barrier material, and an active layer overlying a top surface of the gate electrode, and a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. The dielectric diffusion barrier material is different from the gate dielectric material and is selected from a dielectric metal oxide material and a dielectric compound of silicon, and suppresses loss of metallic elements during subsequent anneal processes.

Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.

Abstract: Provided is an expression vector including a nucleotide sequence for encoding lysine decarboxylase CadA, and a sequence of a constitutive promoter for regulating the expression of the nucleotide sequence. Also provided is a recombinant microorganism including the expression vector and a method of producing 1,5-diaminopentane by using the recombinant microorganism.

Abstract: Aspects of the disclosure provide apparatuses and methods for wireless communications. One apparatus includes processing circuitry that selects one or more first available radio link monitoring reference signal (RLM-RS) samples from a plurality of received RLM-RS samples based on signal qualities of the one or more first available RLM-RS samples. The one or more first available RLM-RS samples are received within a first evaluation period. The processing circuitry determines whether a total number of the one or more first available RLM-RS samples is less than a target number. When the total number of the one or more first available RLM-RS samples is determined to be less than the target number, the processing circuitry determines a second evaluation period that is greater than the first evaluation period, and performs an RLM procedure in an unlicensed band within the second evaluation period.

Abstract: A semiconductor device according to the present disclosure includes a first plurality of gate-all-around (GAA) devices in a first device area and a second plurality of GAA devices in a second device area. Each of the first plurality of GAA devices includes a first vertical stack of channel members extending along a first direction, and a first gate structure over and around the first vertical stack of channel members. Each of the second plurality of GAA devices includes a second vertical stack of channel members extending along a second direction, and a second gate structure over and around the second vertical stack of channel members. Each of the first plurality of GAA devices includes a first channel length and each of the second plurality of GAA devices includes a second channel length smaller than the first channel length.

Abstract: Various novel concepts and schemes pertaining to non-orthogonal multiple access for wireless communications are described. A group orthogonal coded access (GOCA) scheme is introduced to reduce multi-user interference (MUI) and improve performance. A repetition division multiple access (RDMA) scheme is introduced to differentiate user equipment (UEs) by different repetition patterns. A low-density spreading (LDS) scheme is introduced to reduce MUI and improve performance.

Abstract: A wavelength conversion module including an isolation structure layer, multiple wavelength conversion patterns, a dichroic filter film, and at least one dichroic filter layer is provided. The isolation structure layer has multiple openings. The wavelength conversion patterns are disposed in a part of the openings, and configured to absorb a first part of multiple excitation light beams be excited to generate multiple converted light beams. The dichroic filter film is disposed on one side of the isolation structure layer. The at least one dichroic filter layer is disposed on another side of the isolation structure layer or disposed in the openings. A part of the converted light beams are reflected to the wavelength conversion patterns by the dichroic filter film. A second part of the excitation light beams passing through the wavelength conversion patterns are reflected to the wavelength conversion patterns by the at least one dichroic filter layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first nanostructure over the substrate. The semiconductor device structure includes a gate stack over the substrate and surrounding the first nanostructure. The semiconductor device structure includes a first source/drain layer surrounding the first nanostructure and adjacent to the gate stack. The semiconductor device structure includes a contact structure surrounding the first source/drain layer, wherein a first portion of the contact structure is between the first source/drain layer and the substrate.

Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a frontside and a backside. The workpiece includes a substrate, a first plurality of channel members over a first portion of the substrate, a second plurality of channel members over a second portion of the substrate, an isolation feature sandwiched between the first and second portions of the substrate. The method also includes forming a joint gate structure to wrap around each of the first and second pluralities of channel members, forming a pilot opening in the isolation feature, extending the pilot opening through the join gate structure to form a gate cut opening that separates the joint gate structure into a first gate structure and a second gate structure, and depositing a dielectric material into the gate cut opening to form a gate cut feature.

Abstract: A method includes forming a first semiconductor fin and a second semiconductor fin over a substrate; forming an shallow trench isolation (STI) structure on the substrate and between the first semiconductor fin and the second semiconductor fin; forming a spacer layer on the first semiconductor fin, the second semiconductor fin, and the STI structure; patterning the spacer layer to form a spacer extending along the second sidewall of the first semiconductor fin, a top surface of the STI structure, and the second sidewall of the second semiconductor fin; forming a first epitaxy structure in contact with a top surface of the first semiconductor fin and the first sidewall of the first semiconductor fin; and forming a second epitaxy structure in contact with a top surface of the second semiconductor fin and the first sidewall of the second semiconductor fin.

Abstract: The present disclosure relates to an integrated circuit. In one implementation, the integrated circuit may include a semiconductor substrate; at least one source region comprising a first doped semiconductor material; at least one drain region comprising a second doped semiconductor material; at least one gate formed between the at least one source region and the at least one drain region; and a nanosheet formed between the semiconductor substrate and the at least one gate. The nanosheet may be configured as a routing channel for the at least one gate and may have a first region having a first width and a second region having a second width. The first width may be smaller than the second width.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus may be a UE. The apparatus may be a UE. The UE determines to transmit a preamble sequence to a base station at a random access occasion in a random access procedure when the UE is in a connected state. The UE determines that the random access occasion is in a same predetermined time period as an uplink channel or a sounding reference signal that is scheduled to be transmitted to the base station. The UE refrains from transmitting the preamble sequence or refraining from transmitting the uplink channel or the sounding reference signal.

Abstract: A FinFET device includes a fin, an epitaxial layer disposed at a side surface of the fin, a contact disposed on the epitaxial layer and on the fin. The contact includes an epitaxial contact portion and a metal contact portion disposed on the epitaxial contact portion. The doping concentration of the epitaxial contact portion is higher than a doping concentration of the epitaxial layer.

Abstract: A method for fabricating a semiconductor device includes providing a fin in a first region of a substrate. The fin includes a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. A portion of a layer of the second type of epitaxial layers in a channel region of the first fin is removed to form a first gap between a first layer of the first type of epitaxial layers and a second layer of the first type of epitaxial layers. A first portion of a first gate structure is formed within the first gap and extending from a first surface of the first layer of the first type of epitaxial layers to a second surface of the second layer of the first type of epitaxial layers. A first source/drain feature is formed abutting the first portion of the first gate structure.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

Abstract: The invention relates to a photodiode, like an photovoltaic (OPV) cell or photodetector (OPD), comprising, between the photoactive layer and an electrode, a hole selective layer (HSL) for modifying the work function of the electrode and/or the photoactive layer, wherein the HSL comprises a fluoropolymer and optionally a conductive polymer, and to a composition comprising such a fluoropolymer and a conductive polymer.

Abstract: A method for fabricating a semiconductor device having a substantially undoped channel region includes forming a plurality of fins extending from a substrate. In various embodiments, each of the plurality of fins includes a portion of a substrate, a portion of a first epitaxial layer on the portion of the substrate, and a portion of a second epitaxial layer on the portion of the first epitaxial layer. The portion of the first epitaxial layer of each of the plurality of fins is oxidized, and a liner layer is formed over each of the plurality of fins. Recessed isolation regions are then formed adjacent to the liner layer. The liner layer may then be etched to expose a residual material portion (e.g., Ge residue) adjacent to a bottom surface of the portion of the second epitaxial layer of each of the plurality of fins, and the residual material portion is removed.

Abstract: Present disclosure provides a method for forming a semiconductor structure, including forming a dielectric layer over a semiconductor substrate, patterning an insulator stripe over the semiconductor substrate, including forming an insulator layer over the semiconductor substrate and at a bottom of the insulator stripe, depositing a semiconductor capping layer continuously over the insulator stripe, wherein the semiconductor capping layer includes crystalline materials, wherein the semiconductor capping layer is free from being in direct contact with the semiconductor substrate, and cutting off the semiconductor capping layer between the insulator stripes, forming a gate, wherein the gate is in direct contact with the semiconductor capping layer, a first portion of the semiconductor capping layer covered by the gate is configured as a channel structure, and forming a conductible region at a portion of the insulator stripe not covered by the gate stripe by a regrowth operation.

Abstract: The present invention provides an intelligent virtual display device including a contact lens. The contact lens has a central area thereon, a micro display disposed outside the central area, a wearable reflector disposed corresponding to the micro display and configured to receive and to reflect images of the micro display, and a controller. The controller is connected with the micro display and configured to send the control signals to the micro display so as to generate the images. The contact lens is designed for being worn on a user's eyeball. When the eyeball rotates, the micro display changes its projection direction simultaneously to match the user's visual angle.

Abstract: The present invention provides a computer-aided conversion test system and method for generating intelligible speech. The test system includes an acoustic test module with a nasal-genio-oropharyngeal tract, a transmitting module generates a detecting signal, a first receiving module, a second receiving module, and a central processing module with a plurality of first phonetically oral cavity shape spectra. By adjusting the transmitting module, the first receiving module, or the second receiving module, a second phonetically oral cavity shape spectrum is correctly compared and identified by a central computing unit as one of the corresponding first phonetically oral cavity shape spectra. After testing, training and adjusting through the test method, the detecting signal transmitted by the transmitting module is analyzed and identified by the central processing module to increase its interpretation accuracy and shorten the time of machine learning.